AD9144BCPZRL View Datasheet(PDF) - Analog Devices
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AD9144BCPZRL Datasheet PDF : 125 Pages
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AD9144
For a particular application, the number of converters to use (M)
and the fDATA (DataRate) are known. The LaneRate and number
of lanes (L) can be traded off as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate is between 1.44 Gbps and 12.4 Gbps.
Octets per frame per lane (F) and samples per convertor per
frame (S) define how the data is packed. If F = 1, the high density
setting must be set to one (HD = 1). Otherwise, set HD = 0.
Converter resolution and bits per sample (N and NP) must both be
set to 16. Frames per multiframe (K) must be set to 32 for Mode 0,
Mode 4 and Mode 9. Other modes can use either K = 16 or K = 32.
DualLink
DualLink sets up two independent JESD204B links, which allows
each link to be reset independently. If this functionality is desired,
set DualLink to 1; if a single link is desired, set DualLink to 0.
Note that Link 0 and Link 1 must have identical parameters.
The operating modes available when using dual-link mode are
shown in Table 28. In addition to these operating modes, the
modes in Table 28 can also be used when using single-link mode.
Scrambling
Scrambling is a feature that makes the spectrum of the link data
independent. This avoids spectral peaking and provides some
protection against data dependent errors caused by frequency
selective effects in the electrical interface. Set to 1 if scrambling
is being used, or to 0 if it is not.
Subclass
Subclass determines whether the latency of the device is
deterministic, meaning it requires an external synchronization
signal. See the Subclass Setup section for more information.
CurrentLink
Set CurrentLink to either 0 or 1 depending on whether Link 0
or Link 1, respectively, needs to be configured.
Lanes
Lanes is used to enable and deskew particular lanes in two
thermometer coded registers.
Lanes = (2L) − 1.
UnusedLanes
UnusedLanes is used to turn off unused circuit blocks to save
power. Each physical lane that is not being used (SERDINx±)
must be powered off by writing a 1 to the corresponding bit of
Register 0x201.
For example, if using Mode 6 in dual-link mode and sending
data on SERDIN0±, SERDIN1±, SERDIN4±, and SERDIN5±,
set UnusedLanes = 0xCC to power off Physical Lane 2, Lane 3,
Lane 6, and Lane 7.
Data Sheet
CheckSumMode
CheckSumMode must match the checksum mode used on the
transmit side. If the checksum used is the sum of fields in the
link configuration table, CheckSumMode = 0. If summing the
registers containing the packed link configuration fields,
CheckSumMode = 1. For more information on the how to
calculate the two checksum modes, see the Lane0Checksum
section.
Lane0Checksum
Lane0Checksum can be used for error checking purposes
to ensure that the transmitter is set up as expected. Both
CheckSumMode calculations use the fields contained in
Register 0x450 to Register 0x45A. Select whether to sum by
fields or by registers, matching the setting on the transmitter.
If CheckSumMode = 0, the summation is computed by fields.
The checksum is the lower 8 bits of the sum of the DID,
ADJCNT, BID, ADJDIR, PHADJ, LID, Scrambling, L – 1, F − 1,
K − 1, M − 1, CS, N − 1, Subclass, NP − 1, JESDVer, S − 1, HD,
and CF variables.
If CheckSumMode = 1, the summation is computed by registers.
The checksum is the sum of Register 0x450 to Register 0x45A,
Modulo 256.
DAC Power-Down Setup
As described in the Step 1: Start Up the DAC section, PdDACs
must be set to 0 if all 4 converters are being used. If fewer than
four converters are being used, the unused converters must be
powered down. Table 29 can be used to determine which DACs
are powered down based on the number of converters per link
(M) and whether the device is in DualLink mode.
Table 29. DAC Power-Down Configuration Settings
M (Converters
DACs to Power Down
per link)
DualLink 0 1 2 3 PdDACs
1
0
0 1 1 1 0b0111
1
1
0 1 0 1 0b0101
2
0
0 0 1 1 0b0011
2
1
0 0 0 0 0b0000
4
0
0 0 0 0 0b0000
PdClocks
If both DACs in DAC Dual B (DAC2 and DAC3) are powered
down, the clock for DAC Dual B can be powered down. In this
case, PdClocks = 0x40; if not, PdClocks = 0x00.
Rev. B | Page 30 of 125
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