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AD9144BCPAZ View Datasheet(PDF) - Analog Devices

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AD9144BCPAZ Datasheet PDF : 125 Pages
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AD9144
STEP 4: PHYSICAL LAYER
This section describes how to set up the physical layer of the
SERDES interface. In this section, the input termination settings
are configured along with the CDR sampling and SERDES PLL.
STEP 5: DATA LINK LAYER
This section describes how to set up the data link layer of the
SERDES interface. This section deals with SYSREF processing,
setting deterministic latency, and establishing the link.
Table 20. Device Configurations and Physical Layer Settings
Bit
Addr. No. Value1 Variable Description
0x2AA
0x2AB
0xB7
0x87
SERDES interface termination
setting
0x2B1
0x2B2
0xB7
0x87
SERDES interface termination
setting
0x2A7
0x01
Autotune PHY setting
0x2AE
0x01
Autotune PHY setting
0x314
0x01
SERDES SPI configuration
0x230
0x
5
Halfrate Set up CDR; see the SERDES
Clocks Setup section
[4:2] 0x2
SERDES PLL default
configuration
1
OvSmp Set up CDR; see the SERDES
Clocks Setup section
0x206
0x00
Reset CDR
0x206
0x01
Release CDR reset
0x289
0x
2
1
SERDES PLL configuration
[1:0]
PLLDiv Set CDR oversampling for
PLL; see the SERDES Clocks
Setup section
0x284
0x62
Optimal SERDES PLL loop filter
0x285
0xC9
Optimal SERDES PLL loop filter
0x286
0x0E
Optimal SERDES PLL loop filter
0x287
0x12
Optimal SERDES PLL charge
pump
0x28A
0x7B
Optimal SERDES PLL VCO LDO
0x28B
0x00
Optimal SERDES PLL
configuration
0x290
0x89
Optimal SERDES PLL VCO
varactor
0x294
0x24
Optimal SERDES PLL charge
pump
0x296
0x03
Optimal SERDES PLL VCO
0x297
0x0D
Optimal SERDES PLL VCO
0x299
0x02
Optimal SERDES PLL
configuration
0x29A
0x8E
Optimal SERDES PLL VCO
varactor
0x29C
0x2A
Optimal SERDES PLL charge
pump
0x29F
0x78
Optimal SERDES PLL VCO
varactor
0x2A0
0x06
Optimal SERDES PLL VCO
varactor
0x280
0x01
Enable SERDES PLL2
0x268
0x
[7:6]
EqMode See the Equalization Mode
Setup section
[5:0] 0x22
Required value (default)
Table 21. Data Link Layer Settings
Bit
Addr. No. Value1 Variable
0x301
0x
Subclass
0x304
0x
LMFCDel
0x305
0x
LMFCDel
0x306
0x
LMFCVar
0x307
0x
LMFCVar
0x03A
0x01
0x03A
0x03A
SYSREF±
Signal
0x308
to
0x30B
0x334
0x81
0xC1
0x
XBarVals
0x
InvLanes
0x300
0x
6
3
2
CheckSumMode
DualLink
CurrentLink
[1:0]
EnLinks
Description
See the JESD204B
Setup section.
See the Link Latency
Setup section.
See the Link Latency
section.
See the Link Latency
Setup section.
See the Link Latency
Setup section.
Set sync mode =
one-shot sync; see
the Syncing LMFC
Signals section for
other sync options.
Enable the sync
machine.
Arm the sync
machine.
If Subclass = 1, ensure
that at least one
SYSREF± edge is sent
to the device.2
If remapping lanes,
set up crossbar; see
the Crossbar Setup
section.
Invert polarity of
desired logical lanes.
Bit x of InvLanes
must be a 1 for each
Logical Lane x to
invert.
Enable the links.
See the JESD204B
Setup section.
Set to 0 to access
Link 0 status or 1 for
Link 1 status
readbacks. See the
JESD204B Setup
section.
EnLinks = 3 if
DualLink = 1
(enables Link 0 and
Link 1);
EnLinks = 1 if
DualLink = 0 (enables
Link 0 only).
1 0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2 Verify that Register 0x03B[3] reads back 1 after sending at least one SYSREF±
edge to the device to indicate that the LMFC sync machine has properly locked.
1 0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2 Verify that Register 0x281[0] reads back 1 after enabling the SERDES PLL to
indicate that the SERDES PLL has locked.
Rev. B | Page 27 of 125
 

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