datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

AD9144BCPZRL View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9144BCPZRL Datasheet PDF : 125 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
Data Sheet
AD9144
DEVICE SETUP GUIDE
OVERVIEW
The sequence of steps to properly set up the AD9144 is as follows:
1. Set up the SPI interface, power up necessary circuit blocks,
make required writes to the configuration registers, and set
up the DAC clocks (see the Step 1: Start Up the DAC section).
2. Set the digital features of the AD9144 (see the Step 2:
Digital Datapath section).
3. Set up the JESD204B links (see the Step 3: Transport Layer
section).
4. Set up the physical layer of the SERDES interface (see the
Step 4: Physical Layer section).
5. Set up the data link layer of the SERDES interface (see the
Step 5: Data Link Layer section).
6. Check for errors (see the Step 6: Optional Error
Monitoring section).
7. Optionally, enable any needed features as described in the
Step 7: Optional Features section.
The register writes listed in Table 15 to Table 21 give the register
writes necessary to set up the AD9144. Consider printing out
this setup guide and filling in the Value column with appropriate
variable values for the conditions of the desired application.
The notation 0x, shaded in gray, indicates register settings that
must be filled in by the user. To fill in the unknown register
values, select the correct settings for each variable listed in the
Variable column of Table 15 to Table 21. The Description
column describes how to set variables or provides a link to a
section where this is described.
STEP 1: START UP THE DAC
This section describes how to set up the SPI interface, power up
necessary circuit blocks, write required configuration registers,
and set up the DAC clocks, as listed in Table 15.
Table 15. Power-Up and DAC Initialization Settings
Bit
Addr. No. Value1 Variable Description
0x000
0xBD
Soft reset.
0x000
0x3C
Deassert reset, set 4-wire SPI.
0x011
0x
70
Power up band gap.
[6:3]
PdDACs PdDACs = 0 if all 4 DACs are
being used. If not, see the DAC
Power-Down Setup section.
20
Power up master DAC.
0x080
0x
PdClocks PdClocks = 0 if all 4 DACs are
being used. If not, see the DAC
Power-Down Setup section.
0x081
0x
PdSysref PdSysref = 0x00 for Subclass 1.
PdSysref = 0x10 for Subclass 0.
See the Subclass Setup section
for details on subclass.
1 0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
The registers in Table 16 must be written from their default
values to be the values listed in the table for the device to work
correctly. These registers must be written after any soft reset,
hard reset, or power-up occurs.
Table 16. Required Device Configurations
Addr. Value Description
0x12D 0x8B Digital datapath configuration
0x146 0x01 Digital datapath configuration
0x2A4 0xFF Clock configuration
0x232 0xFF SERDES interface configuration
0x333 0x01 SERDES interface configuration
If using the optional DAC PLL, also set the registers in Table 17.
Table 17. Optional DAC PLL Configuration Procedure
Addr. Value1 Variable
Description
0x087 0x62
Optimal DAC PLL loop filter
settings
0x088 0xC9
Optimal DAC PLL loop filter
settings
0x089 0x0E
Optimal DAC PLL loop filter
settings
0x08A 0x12
Optimal DAC PLL charge pump
settings
0x08D 0x7B
Optimal DAC LDO settings for
DAC PLL
0x1B0 0x00
Power DAC PLL blocks when
power machine is disabled
0x1B9 0x24
Optimal DAC PLL charge pump
settings
0x1BC 0x0D
Optimal DAC PLL VCO control
settings
0x1BE 0x02
Optimal DAC PLL VCO power
control settings
0x1BF 0x8E
Optimal DAC PLL VCO calibration
settings
0x1C0 0x2A
Optimal DAC PLL lock counter
length setting
0x1C1 0x2A
Optimal DAC PLL charge pump
setting
0x1C4 0x7E
Optimal DAC PLL varactor
settings
0x08B 0x
LODivMode See the DAC PLL Setup section
0x08C 0x
RefDivMode See the DAC PLL Setup section
0x085 0x
BCount
See the DAC PLL Setup section
Various 0x
LookUpVals See Table 25 in the DAC PLL Setup
section for the list of register
addresses and values for each.
0x083 0x10
Enable DAC PLL2
1 0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register
value.
2 Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to
indicate that the DAC PLL has locked.
Rev. B | Page 25 of 125
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]