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AD9144-M6720-EBZ View Datasheet(PDF) - Analog Devices

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AD9144-M6720-EBZ Datasheet PDF : 125 Pages
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AD9144
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
PVDD12 1
CLK+ 2
CLK– 3
PVDD12 4
SYSREF+ 5
SYSREF– 6
PVDD12 7
PVDD12 8
PVDD12 9
PVDD12 10
TXEN0 11
TXEN1 12
DVDD12 13
DVDD12 14
SERDIN0+ 15
SERDIN0– 16
SVDD12 17
SERDIN1+ 18
SERDIN1– 19
SVDD12 20
VTT 21
SVDD12 22
AD9144
TOP VIEW
(Not to Scale)
66 IOVDD
65 CS
64 SCLK
63 SDIO
62 SDO
61 RESET
60 IRQ
59 PROTECT_OUT0
58 PROTECT_OUT1
57 PVDD12
56 PVDD12
55 GND
54 GND
53 DVDD12
52 SERDIN7+
51 SERDIN7–
50 SVDD12
49 SERDIN6+
48 SERDIN6–
47 SVDD12
46 VTT
45 SVDD12
NOTES
1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No. Mnemonic
Description
1
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
2
CLK+
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input. When
the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be ac-coupled.
3
CLK−
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input. When
the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be ac-coupled.
4
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
5
SYSREF+
Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or
dc-coupled.
6
SYSREF−
Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or
dc-coupled.
7
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
8
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
9
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
10
PVDD12
1.2 V Supply. PVDD12 provides a clean supply.
11
TXEN0
Transmit Enable for DAC0 and DAC1. The CMOS levels are determined with respect to IOVDD.
12
TXEN1
Transmit Enable for DAC2 and DAC3. The CMOS levels are determined with respect to IOVDD.
13
DVDD12
1.2 V Digital Supply.
14
DVDD12
1.2 V Digital Supply.
15
SERDIN0+
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
16
SERDIN0−
Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
17
SVDD12
1.2 V JESD204B Receiver Supply.
18
SERDIN1+
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
19
SERDIN1−
Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Rev. B | Page 12 of 125
 

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