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AD9012TD View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9012TD
ADI
Analog Devices ADI
AD9012TD Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD9012
APPLICATION INFORMATION
The AD9012 is compatible with all standard TTL logic families.
However, to operate at the highest ENCODE rates, the sup-
porting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Which-
ever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.
The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier such
as the AD9610 will be required. For those applications that do
not require the full input bandwidth of the AD9012, some of the
more traditional monolithic amplifiers, such as the AD846,
should work very well. Overall performance with monolithic
amplifiers can be improved by inserting a 40 resistor in series
with the amplifier output.
The output data is buffered through the TTL compatible out-
put latches. In addition to the latch propagation delay (tPD), all
data is delayed by one clock cycle before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL compatible ENCODE signal (see Figure 2).
The AD9012 also incorporates a HYSTERESIS control pin
that provides from 0 mV to 10 mV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INH pin of the AD9012 determines how the
converter handles overrange inputs (AIN + VREF). In the
“enabled” state (floating at –5.2 V), the OVERFLOW INH
output will be at logic HIGH and all other outputs will be at
logic LOW for overrange inputs (return-to-zero operation). In
the “inhibited” state (tied to ground), the OVERFLOW INH
output will be at logic LOW for overrange inputs, and all other
digital outputs will be at logic HIGH (nonreturn-to-zero operation).
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important in
fault sensitive applications, such as digital radio (QAM).
Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly impor-
tant in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.
LAYOUT SUGGESTIONS
Designs using the AD9012, such as all high speed devices, must
follow a few basic layout rules to ensure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention
involves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in improv-
ing the integral linearity by correcting any reference ladder skews.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors should be very effective.
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.
1k
–15V
4k
ANALOG
INPUT
(0 TO +2V)
0.1F
100
2N3906
AD741 10
0.1F
TTL
ENCODE
INPUT
NYQUIST
FILTER
50
50
1.5k
40
AD9611
EQUAL
DISTANCE
–VREF +VREF
OVERFLOW
AIN
D8 (MSB)
D7
AIN
AD9012
D6
D5
D4
ENCODE
D3
D2
D1 (LSB)
+5.0V –5.2V
0.01F 0.1F 0.1F 0.01F
Figure 5. Typical Application
–6–
REV. F
 

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