V53C16128H View Datasheet(PDF) - Mosel Vitelic Corporation
Part Name
Description
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V53C16128H Datasheet PDF : 20 Pages
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MOSEL VITELIC
V53C16128H
HIGH PERFORMANCE
128K x 16 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Extended Data Out Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
30
30 ns
16 ns
12 ns
65 ns
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s 128K x 16-bit organization
s EDO Page Mode for a sustained data rate
of 83 MHz
s RAS access time: 30, 35, 40, 45, 50 ns
s Dual CAS Input
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s Single +5V ±10% Power Supply
s TTL Interface
Description
The V53C16128H is a 131,072 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C16128H offers Page mode with
Extended Data Output. EDO Page Mode operation
allows random access up to 256 x 16 bits, within a
page, with cycle times as short as 12ns. An
address, CAS and RAS input capacitances are
reduced to minimize the loading. The V53C16128H
has asymmetric address, 9-bit row and 8-bit
column.
All inputs are TTL compatible. The V53C16128H
is best suited for graphics, and DSP applications
requiring high performance memories.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
Access Time (ns)
K
T
30 35 40 45 50
•
•
•
•
•
•
•
Power
Std.
•
Temperature
Mark
Blank
V53C16128H Rev. 1.2 July 1997
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