ADP667AN View Datasheet(PDF) - Analog Devices

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ADP667AN

+5 V Fixed, Adjustable Low-Dropout Linear Voltage Regulator

Analog Devices 

ADP667

APPLICATIONS INFORMATION

Circuit Configurations

For a fixed +5 V output the SET input should be grounded, and

no external resistors are necessary. This basic configuration is

shown in Figure 2. The input voltage can range from +5.15 V

to +16.5 V, and output currents up to 250 mA are available

provided that the maximum package power dissipation is not

exceeded.

+

IN

OUT

ADP667

+ C1

10µF

+5V

OUTPUT

SET GND SHDN

Figure 2. Fixed +5 V Output Circuit

Output Voltage Setting

If the SET input is connected to a resistor divider network, the

output voltage is set according to the following equation:

VOUT

= V SET

×

R1 + R2

R1

where VSET = 1.255 V.

VIN

IN

OUT

VOUT

ADP667

R2

+ C1

10µF

SET

R1

SHDN GND

Figure 3. Adjustable Output Circuit

The resistor values may be selected by first choosing a value for

R1 and then selecting R2 according to the following equation:

R2 = R1 × VVOSEUTT

−



1

The input leakage current on SET is 10 nA maximum. This

allows large resistor values to be chosen for R1 and R2 with

little degradation in accuracy. For example, a 1 MΩ resistor

may be selected for R1, and then R2 may be calculated accord-

ingly. The tolerance on SET is guaranteed at less than ± 25 mV,

so in most applications fixed resistors will be suitable.

Shutdown Input (SHDN)

The SHDN input allows the regulator to be switched off with a

logic level signal. This will disable the output and reduce the

current drain to a low quiescent (1 µA maximum) current. This

is very useful for low power applications. Driving the SHDN in-

put to greater than 1.5 V places the part in shutdown.

If the shutdown function is not being used, then SHDN should

be connected to GND.

Low Supply or Low Battery Detection

The ADP667 contains on-chip circuitry for low power supply or

battery detection. If the voltage on the LBI pin falls below the

internal 1.255 V reference, then the open drain output LBO will

go low. The low threshold voltage may be set to any voltage

above 1.255 V by appropriate resistor divider selection.

R3

=

R4

×

 VBATT

 VLBI

–1

where R3 and R4 are the resistive divider resistors and VBATT is

the desired low voltage threshold.

Since the LBI input leakage current is less than 10 nA, large val-

ues may be selected for R3 and R4 in order to minimize loading.

For example, a 6 V low threshold, may be set using 10 MΩ for

R3 and 2.7 MΩ for R4.

The LBO output is an open-drain output that goes low sinking

current when LBI is less than 1.255 V. A pull-up resistor of

10 kΩ or greater may be used to obtain a logic output level with

the pull-up resistor connected to VOUT.

VIN

R3

R4

IN

OUT

ADP667

LBI

LBO

SHDN GND SET

10kΩ

+ C1

10µF

VOUT

LOW BATTERY

STATUS OUTPUT

Figure 4. Low Battery/Supply Detect Circuit

–4–

REV. 0

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