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HA-5020 View Datasheet(PDF) - Intersil

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HA-5020 Datasheet PDF : 23 Pages
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HA-5020
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response
illustrate the performance of the HA-5020 in various closed
loop gain configurations. Although the bandwidth dependency
on closed loop gain isn’t as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s unique
relationship between bandwidth and RF. All current feedback
amplifiers require a feedback resistor, even for unity gain
applications, and RF, in conjunction with the internal
compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HA-5020 design is optimized
for a 1000RF at a gain of +1. Decreasing RF in a unity gain
application decreases stability, resulting in excessive peaking
and overshoot. At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
GAIN (ACL)
-1
+1
+2
+5
+10
-10
RF ()
750
1000
681
1000
383
750
BANDWIDTH
(MHz)
100
125
95
52
65
22
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The use
of low inductance components such as chip resistors and
chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
Attention must be given to decoupling the power supplies. A
large value (10µF) tantalum or electrolytic capacitor in
parallel with a small value (0.1µF) chip capacitor works well
in most cases.
A ground plane is strongly recommended to control noise. Care
must also be taken to minimize the capacitance to ground seen
by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. It is recommended that the
ground plane be removed under traces connected to -IN, and
that connections to -IN be kept as short as possible to minimize
the capacitance from this node to ground.
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
VIN
+-
R
RT
VOUT
CL
RF
RI
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
The selection criteria for the isolation resistor is highly
dependent on the load, but 27has been determined to be
a good starting value.
Enable/Disable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical
specifications table being valid and applicable. When
disabled the amplifier output assumes a true high
impedance state and the supply current is reduced
significantly.
The circuit shown in Figure 7 is a simplified schematic of the
enable/disable function. The large value resistors in series
with the DISABLE pin makes it appear as a current source to
the driver. When the driver pulls this pin low current flows out
of the pin and into the driver. This current, which may be as
large as 350µA when external circuit and process variables
are at their extremes, is required to insure that point “A”
achieves the proper potential to disable the output. The
driver must have the compliance and capability of sinking all
of this current.
+VCC
R6
R10
R33
15K
D1
QP18
R7
ENABLE/
15K
DISABLE INPUT
R8
A
QP3
FIGURE 7. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE
FUNCTION
When VCC is +5V the DISABLE pin may be driven with a
dedicated TTL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D1 will not
turn on, and the TTL gate will sink enough current to keep
point “A” at its proper voltage. When VCC is greater than +5V
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than VCC.
10
FN2845.11
June 5, 2006
 

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