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Z85C3010DEG View Datasheet(PDF) - Zilog

Part Name
Description
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Z85C3010DEG Datasheet PDF : 81 Pages
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CMOS SCC Serial Communications Controller
Product Specification
1
Overview
The features of Zilog’s Z80C30 and Z85C30 devices include:
Z85C30: optimized for nonmultiplexed bus microprocessors
Z80C30: optimized for multiplexed bus microprocessors
Pin-compatible to NMOS versions
Two independent 0 to 4.1Mbps, full-duplex channels, each with separate crystal oscil-
lator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for clock
recovery
Multiprotocol operation under program control; programmable for NRZ, NRZI or FM
data encoding
Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop
Bits Per Character, Programmable Clock Factor, Break Detection and Generation; Par-
ity, Overrun, and Framing Error Detection
Synchronous Mode with Internal or External Character Synchronization on One or
Two Synchronous Characters and CRC Generation and Checking with CRC-16 or
CRC-CCITT Preset to either 1s or 0s
SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Inser-
tion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC
Generation and Checking, and SDLC Loop
Software Interrupt Acknowledge Feature (not available with NMOS)
Local Loopback and Auto Echo Modes
Supports T1 Digital Trunk2
Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit
Byte Counter
Speeds
Z85C3O: 8.5, 10, 16.384MHz
Z80C3O: 8, 10MHz
Other Features for Z85C30 Only
Some of the features listed below are available by default. Some of them (features with *)
are disabled on default to maintain compatibility with the existing Serial Communications
Controller (SCC) design, and “program to enable through WR7”:
PS011706-0511
Overview
 

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