< External video input >
l VSIN (I: Pull Up)
Resets vertical timing function of AVDP6. When this input signal is sampled at intervals equivalent to the width of
horizontal sync pulse signal and low level is detected three times consecutively, this pin resets the internal V counters at
HTL (time where horizontal sync signal starts). This function makes it possible to reset internal V counter synchronizing
with vertical sync signal when composite sync signal is inputted to this pin. At the same time, this function automatically
identifies fields in interlaced scanning mode.
l HSIN (I: Pull Up)
Resets horizontal timing function of AVDP6. AVDP6 samples the input signal synchronizing with the main clock and
sets horizontal scanning time to the horizontal sync start position at the moment the signal falls from high level to low
level, and at the same time, adjust the phase of division clock to HSIN.
l DRI5-0, DGI5-0, DBI5-0 (I: Pull Up)
Digital image signal input pin. This pin becomes valid when internal register R_EIE is “1”. The input data format can
be set to 18 bit RGB, 16 bit YCbCr(ITU601) or ITU656(8bit) depending on the value of internal register R_EIF[1:0].
Input a signal to individual pins as shown below in accordance with the input data format.
18 bit RGB
16 bit YCbCr
Data for capture
SHSIN HSIN for capture
VSIN for capture
Data for BG
HSIN for BG
VSIN for BG
l GCKIN (I)
Clock for external video input is inputted to this pin.
This pin is valid only when GCKS pin is low. Maximum frequency of this signal is 80 MHz.
l GCKS (I: Pull Up)
When external image input signal is present, low level signal is inputted to GCKS pin so that the GCKIN pin input is
used as the video capture clock. When data are displayed on the back drop plane, this signal can be used as dot clock by
using register setting.
When no external image signal is not present, the clock inputted through DCKIN and DCKOUT pins can be used as
GCK by making GCKS open state or high level. In this case, be sure to input a fixed signal to GCKIN pin.