datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

YGV619 View Datasheet(PDF) - LSI Corporation

Part Name
Description
View to exact match
YGV619
LSI
LSI Corporation  LSI
YGV619 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
YGV619
l DREQ (O)
DMA request. This pin is asserted when AVDP6 becomes a state where it can accept the DMA transfer. The DMA
transfer should be performed using regular WRn and RD pins. (Use Dual Address Mode of DMAC)
l RESET (I: Schmidt input)
Initial reset signal input. Inputting this signal clears the internal registers of AVDP6 to initialize the internal state of
the device. (Some registers are loaded with initial value.)
l LEND (I: Pull Up)
Selects an endian of CPU. Big endian is selected when this pin is at high level, or little endian when the level is low.
l SYCKS (I: Pull Up)
Input high level to this pin or leave it open (because it is provided with pull-up resister) when clock inputted through
DCKIN and DCKOUT pins are used as a system clock. VRAM clock and dot clock are generated from DCKIN. At this
time, supply of clock to SYCKIN pin is not needed. Input low level signal to this pin when input clock from SYCKIN and
SYCKOUT pins are used.
< SDRAM interface >
l SDQ31-0 (I/O)
Data bus for SDRAM. AVDP6 uses these pins for data input/out access to SDRAM. The data bus width for SDRAM
can be set to 32 bits or 16 bits by using the register setting. SDQ31-16 pins are not used when SDRAM bus width of 16
bits is used. At this time, SDQ31-16 pins are in output state at all times.
l SA12-0 (O)
Address bus for SDRAM. This bus uses time-sharing method to output row address and column address of SDRAM
used by AVDP6.
l SBA1-0 (O)
Outputs access bank of SDRAM and ACTIVE command at the same time.
SA12-0 and SBA1-0 pins output the signals as shown below depending on the type of SDRAM.
VRM SBA1 SBA0 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
0
- BA -
- BA -
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
1
BA1 BA0
BA1 BA0
- RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
-
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
2
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA -
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
3
- BA -
- BA -
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
4
BA1 BA0
BA1 BA0
-
-
- RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
5
BA1 BA0
BA1 BA0
- RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
-
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
6
- BA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
- BA -
-
-
-
- CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
VRM shows the setting value of R#03:VRM[2:0]. Upper row shows the states of the pins when Active command is
issued, and lower column shows the state when Read/Write command is issued.
l SCS (O)
Outputs chip select signal for SDRAM. A command is issued to SDRAM when this signal is active. When two 16 bit
SDRAMs are used, connect this pin to both SDRAMs.
6
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]