s Pin Functions
< CPU INTERFACE >
l D31-0 (I/O: Pull Up)
CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor.
Unused pins are to be open.
l A23-8 (I: Pull Up), A7-2 (I)
CPU address bus. When accessing CSREG space, signals inputted to A23-8 pins are ignored without regarding to the
bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A7-
2 and A1 / WR3 pin for 16 bit CPU. Systems that control AVDP6 only with CSREG do not use this address bus.
However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when
accessing CSMEM space.
l CSREG (I)
Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is
inputted when the chip select signal is active.
When this signal is low, inputs to A23-8 pins are ignored.
l CSMEM (I)
CSMEM is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory
space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse that is inputted with
this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high
level signal must be inputted to CSMEM in this case.
l LWD (I: Pull Up)
Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or
when low level signal is inputted to this pin, AVDP6 operates as CPU 16 bit device.
l A1 / WR3 , WR2-0 (I)
Controls write access to AVDP6 when chip select input signal is active. A1 / WR3 control D31-24, WR2 controls
D23-16, WR1 controls D15-8, and WR0 controls D7-0.
For 16 bit CPU, A1 / WR3 function as A1 of CPU address. WR2 is not used, and thus must be open because the pin is
provided with a pull-up resistor.
l RD (I)
Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal
and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states
at all times.
l WAIT (O: Pull Up, 3-state output)
Data wait signal output to CPU. When CSREG pin or CSMEM pin (hereafter called “CS pin”) is active, the WAIT
signal is asserted once for RD or A1 / WR3 and WR2-0 signals, and then negated when AVDP6 becomes accessible.
This pin becomes high impedance state when CS pin is not active, and outputs high level signal when CS pin is active
and RD or A1 / WR3 and WR2-0 pins are not active. Use this pin or READY depending on the type of CPU.
l READY (O: Pull Up, 3-state output)
Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high
impedance state when CS pin is not active, outputs high level signal when CS pin is active and RD or A1 / WR3,
WR2-0 pins are not active. Use this pin or WAIT depending on the type of CPU.
l INT (O)
Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the
setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed.