XC2000 View Datasheet(PDF) - Infineon Technologies

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XC2000

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units

Infineon Technologies 

XC2000 Derivatives

System Units (Vol. 1 of 2)

Preliminary

Architectural Overview

2.2

On-Chip System Resources

The XC2000 controllers provide a number of powerful system resources designed

around the CPU. The combination of CPU and these resources results in the high

performance of the members of this controller family.

Peripheral Event Controller (PEC) and Interrupt Control

The Peripheral Event Controller enables response to an interrupt request with a single

data transfer (word or byte) which consumes only one instruction cycle and does not

require saving and restoring the machine status. Each interrupt source is prioritized for

every machine cycle in the interrupt control block. If PEC service is selected, a PEC

transfer is started. If CPU interrupt service is requested, the current CPU priority level

stored in the PSW register is tested to determine whether a higher priority interrupt is

currently being serviced. When an interrupt is acknowledged, the current state of the

machine is saved on the internal system stack and the CPU branches to the system

specific vector for the peripheral.

The PEC contains a set of SFRs which store the count value and control bits for eight

data transfer channels. In addition, the PEC uses a dedicated area of RAM which

contains the source and destination addresses. The PEC is controlled in a manner

similar to any other peripheral: through SFRs containing the desired configuration of

each channel.

An individual PEC transfer counter is implicitly decremented for each PEC service

except in the continuous transfer mode. When this counter reaches zero, a standard

interrupt is performed to the vector location related to the corresponding source. PEC

services are very well suited, for example, to moving register contents to/from a memory

table. The XC2000 has eight PEC channels, each of which offers such fast interrupt-

driven data transfer capabilities.

Memory Areas

The memory space of the XC2000 is configured in a Von Neumann architecture. This

means that code memory, data memory, registers, and IO ports are organized within the

same linear address space which covers up to 16 Mbytes. The entire memory space can

be accessed bytewise or wordwise. Particular portions of the on-chip memory have been

made directly bit addressable as well.

Note: The actual memory sizes depend on the selected device type. This overview

describes the maximum block sizes.

768 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash

memory consists of 3 Flash modules, each organized as 64 4-Kbyte sectors. Each

sector can be separately write protected1), erased and programmed (in blocks of 128

bytes). The complete Flash area can be read-protected. A user-defined password

sequence temporarily unlocks protected areas. The Flash modules combine 128-bit

User’s Manual

ArchitectureX2K, V1.0

2-10

V1.0, 2007-06

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