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22051AKHC View Datasheet(PDF) - Cadeka Microcircuits LLC.

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22051AKHC Datasheet PDF : 84 Pages
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TMC22x5yA
Control Register Map
The TMC22x5yA is initialized and controlled by a set of
registers which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D7-0, is governed by
pins CS, R/W, and A1-0. The serial port is controlled by SDA
and SCL.
Reg Bit Name
Function
Global Control
00 7 SRST
Software reset
00 6 HRST
Hardware reset
00 5-3 SET
SET pin function
00 2 DHVEN
Output H&V sync enable
00 1-0 STD
Selects video standard
Input Processor Control
01 7
reserved, set to zero
01 6 IPMUX
Input mux control
01 5 IP8B
8 bit input format
01 4 TDEN
TRS detect enable
01 3 TBLK
TRS blank enable
01 2 IPCMSB Chroma input msb invert
01 1 ABMUX
AB mux control
01 0 CKSEL
Input clock rate select
Burst Loop Control
02 7 BLLRST BLL auto. reset enable
02 6 VIPEN
Video Input Processor
enable
02 5-4 LOCK
Global lock mode
02 3 BLM
BLL lock mode
02 2 KILD
Color kill disable
02 1 DMODBY Demod bypass
02 0 CINT
CBCR interpolation enable
Chroma Processor Control
03 7-5 BLFS
Burst loop filter select
03 4 CCEN
Chroma coring enable
03 3-2 CCOR
Chroma coring threshold
03 1 GAUBY
Gaussian filter bypass
03 0 GAUSEL Gaussian filter select
Burst Threshold
04 7-0 BTH
Burst threshold
Pedestal
05 7-0 PED
Pedestal level
PRODUCT SPECIFICATION
Reg Bit Name
Function
Luma Processor Control
06 7-6
reserved, set to zero
06 5 ANEN
Adaptive notch enable
06 4 ANR
Adaptive notch rounding
06 3-2 ANT
Adaptive notch threshold
06 1 ANSEL
Adaptive notch select
06 0 NOTCH
Notch enable
Comb Processor Control
07 7 LS1BY
Line store 1 bypass
07 6 LS1IN
Line store 1 input
07 5 LS2DLY
Line store 2 delay
07 4 SPLIT
Line store 2 data width
07 3 BSFBY
Bandsplit filter bypass
07 2 BSFSEL Bandsplit filter select
07 1 BSFMSB
Inverts msb of bandsplit
filter
07 0 GRSDLY
Delays input to GRS
decode by 1H
Mid-Sync Level
08 7-0 MIDS
Mid-sync level
Extended DRS
09 7-4 PCKF
Clock rate
09 3-0 VSTD
Video standard
Output Control
0A 7 OP8B
Output rounded to 8 bits
0A 6-5 OPLMT
Output limit select
0A 4-3 MSEN
Mixed sync enable
0A 2 OPCMSB Chroma output msb invert
0A 1 YBAL
Luma color correction
0A 0 BUREN
Output burst enable
0B 7 FMT422
Enables CBCR output mux
0B 6 CDEC
CBCR decimation enable
0B 5 YUVT
Enables D1 output
0B 4-2
reserved, set to zero
0B 1 DRSEN
DRS output enable
0B 0 DRSCK
DRS data rate
Comb Filter Control
0C 7-6 ADAPT
Adaption mode
0C 5 YCES
YC input error signal
control
0C 4 YCSEL
luma/chroma comb filter
select
0C 3-0 COMB
Comb filter architecture
8
REV. 1.0.0 2/4/03
 

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