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22051AKHC View Datasheet(PDF) - Cadeka Microcircuits LLC.

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Description
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22051AKHC Datasheet PDF : 84 Pages
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TMC22x5yA
PRODUCT SPECIFICATION
Control Register Denitions (continued)
Test Control (3D-3E)
7
6
5
4
3
2
1
0
TEST
Reg Bit
3D-3E 7-0
Name
TEST
Description
Must be set to zero. Auto increment stops at 3F
Test Control (3F)
7
VBIT20
6
PEDDIS
Reg Bit
3F
7
Name
VBIT20
3F
6
3F
5
PEDDIS
CCDEN5
3F
4
CCDEN4
3F
3
CCDEN3
3F
2
CCDEN2
3F
1
CCDEN1
3F
0
CCDEN0
5
CCDEN5
4
CCDEN4
3
CCDEN3
2
CCDEN2
1
CCDEN1
0
CCDEN0
Description
VBIT20 enable. When HIGH the V bit within embedded TRS words is
extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line
16 for NTSC. The PAL operation is unaffected by this register bit.
Pedestal disable. When HIGH, pedestal is not removed from lines with
LID = 00 to 06, lines 0 through 16
Closed caption data enable 5. When HIGH, enables NTSC line 21 field 0
or PAL line 22 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 4. When HIGH, enables NTSC line 22 field 0
or PAL line 23 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 3. When HIGH, enables NTSC line 23 field 0
or PAL line 24 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 2. When HIGH, enables NTSC line 283 field 1
or PAL line 334 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 1. When HIGH, enables NTSC line 284 field 1
or PAL line 335 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 0. When HIGH, enables NTSC line 285 field 1
or PAL line 336 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Status - Read Only (40)
7
6
Reg Bit
40
7-0
Name
DDSPH
5
4
3
2
1
0
DDSPH
Description
DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal
DDS.
36
REV. 1.0.0 2/4/03
 

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