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THC63LVD823 View Datasheet(PDF) - THine Electronics, Inc.

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THC63LVD823 Datasheet PDF : 16 Pages
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THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
PLL requires No external components
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
Supports Single Link, Dual-in (TTL)/Single-out
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT
1st DATA
RED1 8
GREEN1 8
BLUE1 8
HSYNC
VSYNC
DE
2nd DATA
RED2 8
GREEN2 8
BLUE2 8
TRANSMITTER CLOCK IN
(25 to 85MHz)
R/F
/PDWN
8
8
8
PLL
LVDS OUTPUT
TA1 +/-
TB1 +/-
TC1 +/-
1st Link
TD1 +/-
TCLK1 +/-
(25 to 135MHz)
TA2 +/-
TB2 +/-
TC2 +/-
2nd Link
TD2 +/-
TCLK2 +/-
(25 to 85MHz)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
 

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