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TDA1517ATW View Datasheet(PDF) - NXP Semiconductors.

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Description
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TDA1517ATW
NXP
NXP Semiconductors. NXP
TDA1517ATW Datasheet PDF : 19 Pages
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NXP Semiconductors
8 W BTL or 2 × 4 W SE power amplifier
Product specification
TDA1517ATW
The formula for the cut-off frequency at the input is as
follows:
fIC
=
--------------1----------------
2 × π × RiCi
thus
fIC
=
--------------------------------------1---------------------------------------
2 × π × 30 × 103 × 470 × 109
=
11 Hz
As can be seen it is not necessary to use high capacitor
values for the input; so the delay during switch-on, which
is necessary for charging the input capacitors, can be
minimized. This results in a good low frequency response
and good switch-on behaviour.
In stereo applications (single-ended) coupling capacitors
on both input and output are necessary. It should be noted
that the outputs of both amplifiers are in opposite phase.
Built-in protection circuits
The IC contains two types of protection circuits:
Short-circuits the outputs to ground, the supply to
ground and across the load: short-circuit is detected and
controlled by a SOAR protection circuit
Thermal shut-down protection: the junction temperature
is measured by a temperature sensor. Thermal foldback
is activated at a junction temperature of >150 °C.
Output power
The output power as a function of supply voltage has been
measured on the output pins and at THD = 10%. The
maximum output power is limited by the maximum
allowable power dissipation and the maximum available
output current, 2.5 A repetitive peak current.
Supply voltage ripple rejection
The SVRR has been measured without an electrolytic
capacitor on pin 5 and at a bandwidth of 10 Hz to 80 kHz.
The curves for operating and mute condition (respectively)
were measured with Rsource = 0 Ω. Only in single-ended
applications is an electrolytic capacitor (e.g. 100 μF) on
pin 5 necessary to improve the SVRR behaviour.
Headroom
A typical music CD requires at least 12 dB (is factor 15.85)
dynamic headroom (compared with the average power
output) for passing the loudest portions without distortion.
The following calculation can be made for this application
at VP = 12 V and RL = 8 Ω: Po at THD = 0.1% is
approximately 5 W (see Fig.7).
Average listening level without any distortion yields:
PALL
=
----P----t--o---t---
factor
=
------5--------
15.85
=
315 mW
The power dissipation can be derived from Fig.11 for 0 dB
and 12 dB headroom.
Table 1 Power rating
RATING
Po = 5 W
(THD = 0.1%)
HEADROOM
0 dB
12 dB
POWER
DISSIPATION
3.5 W
2.0 W
Thus for the average listening level (music power) a power
dissipation of 2.0 W can be used for the thermal PCB
calculation; see Section “Thermal behaviour (PCB design
considerations)”.
Mode pin
For the 3 functional modes: standby, mute and operate,
the MODE pin can be driven by a 3-state logic output
stage, e.g. a microcontroller with some extra components
for DC-level shifting; see Fig.10 for the respective
DC levels.
Standby mode is activated by a low DC level between
0 and 2 V. The power consumption of the IC will be
reduced to <0.12 mW.
Mute mode is activated by a DC level between
3.3 and 6.4 V. The outputs of the amplifier will be muted
(no audio output); however the amplifier is DC biased
and the DC level of the output pins stays at half the
supply voltage. The input coupling capacitors are
charged when in mute mode to avoid pop-noise.
The IC will be in the operating condition when the
voltage at pin MODE is between 8.5 V and VCC.
Switch-on/switch-off
To avoid audible plops during switch-on and switch-off of
the supply voltage, the MODE pin has to be set in standby
condition (VCC level) before the voltage is applied
(switch-on) or removed (switch-off). The input and SVRR
capacitors are smoothly charged during mute mode.
The turn-on and turn-off time can be influenced by an
RC-circuit connected to the MODE pin. Switching the
device or the MODE pin rapidly on and off may cause ‘click
and pop’ noise. This can be prevented by proper timing on
the MODE pin. Further improvement in the BTL application
can be obtained by connecting an electrolytic capacitor
(e.g. 100 μF) between the SVRR pin and signal ground.
2001 Apr 17
9
 

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