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108296138 View Datasheet(PDF) - Agere -> LSI Corporation

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108296138 Datasheet PDF : 112 Pages
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Advance Data Sheet
November 1999
Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.1 Memory Architecture (continued)
H-BUS:
EVEN STREAMS
A12 = 0
A0 = 0
H-BUS:
ODD STREAMS
1 = 01
A12 = 0
A0 = 1
LOCAL 0—15
A12:A11 = 11
ADDRESS
A
A
11 ………………… 1
TAG
T
T
7 ……………… 0
0
CAM-E
CE-SRAM
READ/WRITE
VALID ENTRY MARKER
PATTERN/NORMAL
DATA SRAM SELECT
PATTERN MODE
OUTPUTS TAG
TO H-BUS
READ/WRITE AND
SRAM SELECT
ADDRESS
A
A
11 ………………… 1
255
0
TAG
T
T
7 ……………… 0
D
DD
D
7 ……………… 0 7 ……………… 0
0
CAM-O
CO-SRAM
H-BUS
ADDRESS
A
A
10 ………………… 0
255
TAG
T
T
7 ……………… 0
0
CAM-L
CL-SRAM
255
THIS IS THE H-BUS CONNECTION MEMORY:
3 CAMS, MAXIMUM OF 48 ACCESSES PER 976 ns
TIME SLOT, REQUIRES <20 ns/ACCESS
LOCAL I/O
PATTERN MODE
OUTPUTS TAG
TO LOCAL OUT
Figure 9. CAM Architecture
DATA SRAM
255
DATA BUFFER 0 DATA BUFFER 1
THIS IS THE H-BUS DATA MEMORY:
EFFECTIVE ACCESS TIME < 10 ns
5-6108F
The maximum number of connections is set by the number of locations in the data SRAM and the CAMs. In this
implementation, 512 simplex (T8102, T8105 only) connections are permitted. Since one connection requires two
CAM entries pointing to a common data location, the maximum number of connections could be reduced to 256
simplex if all connection entries reside within only one CAM. The maximum number of connections is increased
above 512 simplex if the connection type is broadcast, i.e., from one to many.
Lucent Technologies Inc.
31
 

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