Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
Figure 3 shows a block diagram of the TSI devices. The devices operate on a 3.3 V supply for both the core and
I/Os, though the I/Os are TTL compatible and 5 V tolerant.
H.100, H.110, H-MVIP, MVIP, SC-BUS
S/P AND P/S CONVERTERS
512*
LOCATION
DATA
SRAM
LOCAL IN
INPUT
LOGIC
AND S/P
CONVERT
THREE 512*
LOCATION
CONNECTION
CAMs
1024†
LOCATION
DATA
MEMORY
OUTPUT
LOGIC
AND P/S
CONVERT
LOCAL OUT
INTERNAL
ADDRESS
AND
CONTROL
ADDR[1:0]
DATA[7:0]
MICROPROCESSOR
INTERFACE
1024†
LOCATION
CONNECTION
MEMORY
INTERNAL
CLOCKS AND
STATE
COUNTER
TIMING AND
CONTROL
INTERNAL
DATA
FRAME GROUP
INTERFACE
LOGIC
FRAME
GROUPS
…
µP CONTROLS
…
MISC. I/O
…
CLOCKS AND REFS
* For T8100 and T8100A, there are only 256 locations.
† T8102 does not have local data memory.
Figure 3. Block Diagram of the TSI Devices
5-6101.a (F)
14
Lucent Technologies Inc.