SMP04EQ View Datasheet(PDF) - Analog Devices

Part Name

Description

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SMP04EQ

CMOS Quad Sample-and-Hold Amplifier

Analog Devices 

+15V

0.1␮F

SMP04

10-BIT

COUNTER

+5V

DB9

DB2–DB9

DB2

A1 VDD

A0

1/4 DAC8426

MSB

VREF

OUT

DAC C

OUT

LSB

VSS

AGND DGND WR

CLOCK

GENERATOR

ANALOG

RETURN

DIGITAL

RETURN

DB0

DB1

1/4 AD7432

0.1␮F–1␮F CERAMIC

VIN

VOUT

S/H

1/4 SMP04

DGND VSS

VDD

1␮F

+15V

AGND

DEGLITCH LOGIC 1/4 AD7400

Figure 25. DAC Deglitcher

D/A CONVERTER DEGLITCHER

Most D/A converters output an appreciable amount of glitch

energy during a transition from one code to another. The glitch

amplitude can range from several millivolts to hundreds of milli-

volts. This may become unacceptable in many applications. By

selectively delaying the DAC’s output transition, the SMP04

can be used to smooth the output waveform. Figure 25 shows

the schematic diagram of such a deglitcher circuit. Two simple

logic gates (an OR and a NAND gate) provide the proper timing

sequence for the DAC WR strobe and the S/H control signal to

the SMP04. In this example a linear ramp signal is generated by

feeding the most significant eight bits of the 10-bit binary

counter to the DAC. The two least significant bits are used to

produce the delayed WR strobe and the S/H control signals.

Referring to Figure 26a, new data to the DAC input is set up at

the S/H’s falling edge, but the DAC output does not change

until a WR strobe goes active. During this period, the SMP04 is

in a sample mode whose output tracks the DAC output. When

S/H goes HIGH, the current DAC output voltage is held by the

SMP04. After 1.2 µs settling, the WR strobe goes LOW to allow

the DAC output to change. Any glitch that occurs at the DAC

output is effectively blocked by the SMP04. As soon as the WR

strobe goes HIGH, the digital data is latched; at the same time

the S/H goes LOW, allowing the SMP04 to track to the new

DAC output voltage.

Figure 26b shows the deglitching operation. The top trace

shows the DAC output during a transition, while the bottom

trace shows the deglitched output of the SMP04.

DB0

DB1

WR

5V

1␮s

S/H

a.

DLY 627.4␮s

50m

1␮s

b.

Figure 26. (a) Shows the Logic Timing of the Deglitcher.

The Top Two Traces Are the Two Least Significant Bits,

DB0 and DB1, Respectively. These Are Used to Generate

the WR and S/H Signals Which Are Shown in the Bottom

Two Traces. (b) Shows the Typical Glitch Amplitude of a

DAC (Top Trace) and the Deglitched Output of the AMP04

(Bottom Trace).

REV. D

–13–

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