SLA24C164-D View Datasheet(PDF) - Siemens AG

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Description

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SLA24C164-D

8/16 Kbit 1024/2048 x 8 bit Serial CMOS EEPROMs/ I2C Synchronous 2-Wire Bus

Siemens AG 

SLx 24C164

6.2 Current Address Read

The EEPROM content is read without setting an EEPROM address, in this case the

current content of the address counter will be used (e.g. to continue a previous read

operation after the Master has served an interrupt).

Transmission of CSR

Transmission of

EEPROM Data

STOP Condition from

Master

For a current address read the master generates a START

condition, which is followed by the command byte CSR (chip

select read). The receipt of the CSR-byte is acknowledged by

the EEPROM with a low on the SDA line.

During the next eight clock pulses the EEPROM transmits the

data byte and increments the internal address counter.

During the following clock cycle the masters releases the bus

and then transmits the STOP condition.

S

T

S

Bus Activity A Command Byte

T

Master

R

CSR

O

T

P

SDA Line S

1

P

Bus Activity

EEPROM

A Data Byte

C

K

IED02132

Figure 12

Current Address Read

Semiconductor Group

16

1998-07-27

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