S3067 View Datasheet(PDF) - Unspecified

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

S3067 TRANSCEIVER

FUNCTIONAL DESCRIPTION

Transmitter Operation

The S3067 transceiver chip performs the serialization

stage in the processing of a transmit SONET STS-48/

STS-24/STS-12/STS-3/GBE/FC data stream depend-

ing on the data rate selected. It converts 16-bit

parallel data to bit serial format.

A high-frequency bit clock can be generated from a

131.25 MHz to 178 MHz frequency reference by us-

ing an integral frequency synthesizer consisting of a

phase-locked loop circuit with a divider in the loop.

Diagnostic loopback (transmitter to receiver) and line

loopback (receiver to transmitter) is provided. See

Other Operating Modes.

The bypass signal selects between the BYPASSCLK

and the VCO clock. BYPASSCLK can be used to pro-

vide an alternative clock to the internal VCO when the

user selects an error correcting capability which is not

provided by the S3067 dividers. The user must pro-

vide the required frequency for the BYPASSCLK

when error-correcting capability of 6/5/4/3 bytes per

255-byte block is selected.

Clock Synthesizer

The clock synthesizer, shown in the block diagrams

of Figures 4 and 5, is a monolithic PLL that gener-

ates the serial output clock frequency locked to the

input Reference Clock (REFCLKP/N).

The REFCLKP/N input must be generated from a

crystal oscillator that has a frequency accuracy bet-

ter than the value stated in Table 10 in order for the

TSCLK frequency to have the accuracy required for

operation in a SONET system. Lower-accuracy crys-

tal oscillators may be used in applications less

demanding than SONET/SDH.

The on-chip PLL consists of a phase detector, which

compares the phase relationship between the VCO

output and the REFCLKP/N input, a loop filter which

converts the phase detector output into a smooth DC

voltage, and a VCO, whose frequency is varied by

this voltage.

The divide by ‘N’ and divide by ‘M’ provide the

counters required to support error correcting capabil-

ity. The values of ‘N’ and ‘M’ can be selected by

FECSEL lines.

The loop filter generates a VCO control voltage

based on the average DC level of the phase discrimi-

nator output pulses. A single external clean-up

capacitor is utilized as part of the loop filter. The loop

filter’s corner frequency is optimized to minimize out-

put phase jitter.

Timing Generator

The timing generation function, seen in Figure 4,

provides a divide-by-16 version of the transmit serial

clock. This circuitry also provides an internally gen-

erated load signal, which transfers the PIN[15:0]

data from the parallel input register to the serial shift

register.

The PCLK output is a divide-by-16 rate version of

transmit serial clock (divide-by-16). PCLK is in-

tended for use as a divide-by-16 clock for upstream

multiplexing and overhead processing circuits. Using

PCLK for upstream circuits will ensure a stable fre-

quency and phase relationship between the data

coming into and leaving the S3067 device.

The timing generator also produces a feedback ref-

erence clock to the clock synthesizer. A counter

divides the synthesized clock down to the same fre-

quency as the reference clock REFCLK. The PLL in

the clock synthesizer maintains the stability of the

synthesized clock by comparing the phase of the

internal clock with that of the Reference Clock

(REFCLK).

Table 5. Reference Jitter Limits

Operating Mode Band Width RMS Jitter

STS-48

12 kHz to 20 MHz -61 dBc

STS-24

12 kHz to 10 MHz 2 ps

STS-12

12 kHz to 5 MHz 4 ps

STS-3

12 kHz to 1 MHz 16 ps

6

September 17, 2002/ Revision A

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