datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

89LPC933 View Datasheet(PDF) - Philips Electronics

Part Name
Description
View to exact match
89LPC933 Datasheet PDF : 75 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 6: Special function registers - P89LPC935/936 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
TL2
CCU timer low
CCH
00
0000 0000
TMOD Timer 0 and 1 mode
89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00
0000 0000
TOR2H CCU reload register high
CFH
00
0000 0000
TOR2L CCU reload register low
CEH
00
0000 0000
TPCR2H Prescaler control register high CBH
-
-
-
-
-
-
TPCR2H. TPCR2H. 00
xxxx xx00
1
0
TPCR2L Prescaler control register low CAH TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. 00
7
6
5
4
3
2
1
0
0000 0000
TRIM
Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[6] [5]
WDCON Watchdog control register
A7H PRE2 PRE1 PRE0
-
-
WDRUN WDTOF WDCLK
[7] [5]
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1 Watchdog feed 1
C2H
WFEED2 Watchdog feed 2
C3H
[1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2] All ports are in input only (high-impedance) state after power-up.
[3] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[4] The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[5] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7] The only reset source that affects these SFRs is power-on reset.
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]