OP484FP View Datasheet(PDF) - Analog Devices
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OP484FP Datasheet PDF : 24 Pages
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OP184/OP284/OP484
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to
GND
Storage Temperature Range
P-Suffix, S-Suffix Packages
Operating Temperature Range
OP184/OP284/OP484E/OP484F
Junction Temperature Range
P-Suffix, S-Suffix Packages
Lead Temperature
(Soldering 60 sec)
Rating
±18 V
±18 V
±0.6 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
1 For input voltages greater than 0.6 V, the input current should be limited to
less than 5 mA to prevent degradation or destruction of the input devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for device in socket for CERDIP and PDIP. θJA is
specified for device soldered in circuit board for SOIC packages.
Table 5. Thermal Resistance
Package Type
θJA
θJC
8-Lead PDIP (P-Suffix)
103
43
8-Lead SOIC (S-Suffix)
158
43
14-Lead PDIP (P-Suffix)
83
39
14-Lead SOIC (S-Suffix)
92
27
Unit
°C/W
°C/W
°C/W
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
RB1
R3
R4 QB6
QB5
RB3
RB4
VCC
R11
TP
JB1
CB1 N+
M P+
QB1
QL1
Q1 Q3
–IN
QB2
QL2
RB2
QB3
R1
JB2
Q4 Q2
+IN
Q12
Q11
Q8
Q7
QB9
Q16
Q17
Q9
Q5
Q6
QB10
Q10
CC2
C FF
R6
CO
OUT
Q18
QB4
R2
CC1
QB7
R5
R7
QB8
Q13 Q14
Q15
R8
R9
R10
VEE
Figure 4. Simplified Schematic
Rev. D | Page 6 of 24
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