MC14572UBD(2006) View Datasheet(PDF) - ON Semiconductor
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MC14572UBD Datasheet PDF : 6 Pages
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MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
Features
• Diode Protection on All Inputs
• Single Supply Operation
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter
• NAND Input Pin Adjacent to VDD Pin to Simplify Use As An
Inverter
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application
• NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout − 0.5 to VDD V
+ 0.5
Input or Output Current (DC or Transient) Iin, Iout
±10
mA
per Pin
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125 °C
Storage Temperature Range
Tstg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
1
1
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
16
MC14572UBCP
AWLYYWWG
CASE 648
1
SOIC−16 16
D SUFFIX
CASE 751B
1
14572UBG
AWLYWW
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14572UB
ALYWG
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
MC14572UBCP
MC14572UBCPG
MC14572UBD
PDIP−16
PDIP−16
(Pb−Free)
SOIC−16
25 Units / Rail
25 Units / Rail
48 Units / Rail
MC14572UBDG
MC14572UBDR2
SOIC−16 48 Units / Rail
(Pb−Free)
SOIC−16 2500/Tape & Reel
MC14572UBDR2G SOIC−16 2500/Tape & Reel
(Pb−Free)
MC14572UBF
SOEIAJ−16 50 Units / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 6
Publication Order Number:
MC14572UB/D
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