ML145026, ML145027, ML145028
LANSDALE Semiconductor, Inc.
Page 11 of 19
NO
HAS
THE TRANSMISSION
BEGUN?
YES
DOES
THE 5–BIT
ADDRESS MATCH
NO
THE ADDRESS
PINS?
YES
STORE
THE
4–BIT
DATA
DOES
THIS DATA
NO
MATCH THE PREVIOUSLY
STORED
DATA?
YES
IS THIS
AT LEAST THE
2ND CONSECUTIVE
NO
MATCH SINCE VT
DISABLE?
YES
LATCH DATA
ONTO OUTPUT
PINS AND
ACTIVATE VT
DISABLE VT
ON THE 1ST
ADDRESS MISMATCH
DISABLE VT
ON THE 1ST
DATA MISMATCH
HAVE
4–BIT TIMES
YES
PASSED?
NO
HAS
NO
A NEW
TRANSMISSION
BEGUN?
YES
DISABLE
VT
Figure 13. ML145027 Flowchart
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