M13S64164A View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.

Part Name

Description

View to exact match

M13S64164A

1M x 16 Bit x 4 Banks Double Data Rate SDRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M13S64164A

Operation Temperature Condition -40°C~85°C

Self Refresh

A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the

clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the

self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce

power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP

command and then asserting CKE high for longer than tXSRD for locking of DLL.

CLK

CLK

COMMAND

CKE

Sel f

Ref res h

Au to

Refresh

tXSNR

tXSRD

Read

Note：After self refresh exit, input an auto refresh command immediately.

Power down

Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are

idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is

referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.

For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must

be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,

power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred

over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs

of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is

registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.

CLK

CLK

tIS

CKE

COMMAND

VALID

NOP

No column

in

acess

pr ogr am

Enter

p ow er -dow n

mode

tIS

NOP

VALID

Exit power-down

mode

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2009

Revision : 1.0

26/49

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