Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive edge-trigger
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
VCC(V)
1.2
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
Figures, 1, 3
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
tPHL/tPLH
Propagation delay
nSD to nQ, nQ
Figures 2, 3
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
tPHL/tPLH
Propagation delay
nRD to nQ, nQ
Figures 2, 3
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
tW
Clock pulse width
HIGH to LOW
Figure 1
2.7
3.0 to 3.6
4.5 to 5.5
2.0
tW
Set or reset pulse
width LOW
Figure 2
2.7
3.0 to 3.6
4.5 to 5.5
1.2
trem
Removal time
set or reset
Figure 2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
tsu
Set-up time
nD to nCP
Figure 1
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
th
Hold time
nD to nCP
Figure 1
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
fmax
Maximum clock
pulse frequency
Figure 1
2.7
3.0 to 3.6
4.5 to 5.5
NOTE:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
3. Typical value measured at VCC = 5.0V.
1998 Apr 20
6
Product specification
74LV74
LIMITS
–40 to +85 °C
MIN TYP1 MAX
–
70
–
–
24
44
–
18
28
–
132
26
–
9.53
17
–
90
–
–
31
46
–
23
34
–
172
27
–
123
19
–
90
–
–
31
46
–
23
34
–
172
27
–
123
19
34
10
–
25
8
–
20
72
–
15
63
–
34
10
–
25
8
–
20
72
–
15
63
–
–
5
–
14
2
–
10
1
–
8
12
–
6
13
–
–
10
–
22
4
–
12
3
–
8
22
–
6
12
–
–
–10
–
3
–2
–
3
–2
–
3
–22
–
3
–23
–
14
40
–
50
90
–
60
1002
–
70
1103
–
LIMITS
–40 to +125 °C
MIN MAX
–
–
–
56
–
41
–
33
–
23
–
–
–
58
–
43
–
34
–
24
–
–
–
58
–
43
–
34
–
24
41
–
30
–
24
–
18
–
41
–
30
–
24
–
18
–
–
–
15
–
11
–
9
–
7
–
–
–
26
–
15
–
10
–
8
–
–
–
3
–
3
–
3
–
3
–
12
–
40
–
48
–
56
–
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz