Serial Data Timing Diagram
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is
sent from the shift registers to an actual counter. A slew rate of at least 30 V/μs is recommended for these signals. After the
programming is complete, the CLK, DATA, and LE signals should be returned to a low state. Although it is strongly recommended
to keep LE low after programming, LE can be kept high if bit R5 is changed to 0 (from its default value of 1). If this bit is changed,
then the operation of the part is not guaranteed because it is not tested under these conditions. If the CLK and DATA lines are
toggled while the in VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may
be degraded during the time of this programming.