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ISL21009CMB850EP View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL21009CMB850EP High Voltage Input Precision, Low Noise FGA™ Voltage References Intersil
Intersil Intersil
ISL21009CMB850EP Datasheet PDF : 14 Pages
First Prev 11 12 13 14
ISL21009MEP
Board Mounting Considerations
For applications requiring the highest accuracy, board
mounting location should be reviewed. The device uses a
plastic SOIC package, which will subject the die to mild
stresses when the PC board is heated and cooled, slightly
changing the shape. Placing the device in areas subject to
slight twisting can cause degradation of the accuracy of the
reference voltage due to these die stresses. It is normally
best to place the device near the edge of a board, or the
shortest side, as the axis of bending is most limited at that
location. Mounting the device in a cutout also minimizes flex.
Obviously mounting the device on flexprint or extremely thin
PC material will likewise cause loss of reference accuracy.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 4.5µVP-P. The noise measurement is made with a
bandpass filter made of a 1-pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.
Noise in the 10kHz to 1MHz bandwidth is approximately
40µVP-P with no capacitance on the output. This noise
measurement is made with a 2 decade bandpass filter made
of a 1-pole high-pass filter with a corner frequency at 1/10 of
the center frequency and 1-pole low-pass filter with a corner
frequency at 10x the center frequency. Load capacitance up
to 1000pF can be added but will result in only marginal
improvements in output noise and transient response. The
output stage of the ISL21009MEP is not designed to drive
heavily capactive loads, so for load capacitances above
0.001µF, the noise reduction network shown in Figure 44 is
recommended. This network reduces noise significantly over
the full bandwidth. Noise is reduced to less than 20µVP-P from
1Hz to 1MHz using this network with a 0.01µF capacitor and a
2kΩ resistor in series with a 10µF capacitor. Also, transient
response is improved with higher value output capacitor. The
0.01µF value can be increased for better load transient
response with little sacrifice in output stability.
.
VIN = 5.0V
0.1µF
10µF
VIN
VO
ISL21009-25EP
GND
0.01µF
2kΩ
10µF
Turn-On Time
The ISL21009MEP devices have low supply current and
thus the time to bias up internal circuitry to final values will
be longer than with higher power references. Normal turn-on
time is typically 100µs. This is shown in Figure 11. Circuit
design must take this into account when looking at power-up
delays or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, take the
total variation, (VHIGH – VLOW), and divide by the temperature
extremes of measurement (THIGH – TLOW). The result is
divided by the nominal reference voltage (at T = +25°C) and
multiplied by 106 to yield ppm/°C. This is the “Box” method for
specifying temperature coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by
placing a potentiometer from VOUT to GND and connecting the
wiper to the TRIM pin. The TRIM input is high impedance so no
series resistance is needed. The resistor in the potentiometer
should be a low tempco (<50ppm/°C) and the resulting voltage
divider should have very low tempco <5ppm/°C. A digital
potentiometer such as the ISL95810 provides a low tempco
resistance and excellent resistor and tempco matching for trim
applications.
FIGURE 44. HANDLING HIGH LOAD CAPACITANCE
11
FN6744.0
December 15, 2008
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