7083A1K View Datasheet(PDF) - Fairchild Semiconductor
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7083A1K Datasheet PDF : 16 Pages
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ILC7083/ILC7084
The Effects of ESR (Equivalent Series
Resistance)
The ESR of a capacitor is a measure of the resistance due to
the leads and the internal connections of the component.
Typically measured in mΩ (milli-ohms) it can increase to
ohms in some cases.
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; VOUT
and VREF.
With reference to the block diagram in Figure 4, VOUT is fed
back to the error amplifier and is used as the supply voltage
for the internal components of the ILC7083/ILC7084. So
any change in VOUT will cause the error amplifier to try to
compensate to maintain VOUT at the set level and noise on
VOUT will be reflected into the supply of each internal
components of the ILC7083/ILC7084. So any change in
VOUT will cause the error amplifier to try to compensate to
maintain VOUT at the set level and noise on VOUT will be
reflected into the supply of each internal circuit. The refer-
ence voltage, VREF, is influenced by the CNOISE pin. Noise
into this pin will add to the reference voltage and be fed
through the circuit. These factors will not cause a problem if
some simple steps are taken. Figure 5 shows where these
added ESR resistances are present in the typical LDO circuit.
VOUT IOUT
IC
COUT
RC 5 SOT-23-5 4
ILC7083
R*
CNOISE
VIN
1
23
R*
CIN
RF LDOTM
Regulator
ON
OFF
Figure 5. ESR Present in COUT and CNOISE
With this in mind low ESR components will offer better
performance where the LDO may be subjected to large load
transients current. ESR is less of a problem with CIN as the
voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7083/ILC7084 will yield outstanding performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full advan-
tage of any high performance LDO regulator requires paying
careful attention to grounding and printed circuit board
(PCB) layout.
VOUT IOUT
I1
COUT
RPCB
RPCB
5 SOT-23-5 4
ILC7083
ESR
CNOISE
VIN
CIN
1
RPCB
23
RPCB
ON
OFF
Figure 6. Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB
layout magnified by the ESR and PCB resistances and
the accumulation of current flows.
Note that particularly during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and CNOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between COUT, CNOISE and the LDO regulator’s ground pin
will degrade performance of the LDO.
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator.
Note that the key difference here is that COUT and CNOISE are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
8
REV. 1.0.9 1/28/03
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