LF-H41S View Datasheet(PDF) - Micrel

Part Name

Description

View to exact match

LF-H41S

10Base-T/100Base-TX Physical Layer Transceiver

Micrel 

Micrel, Inc.

KSZ8041NL/RNL

List of Figures

Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 22

Figure 2. KSZ8041NL RMII Interface................................................................................................................................... 27

Figure 3. KSZ8041RNL RMII Interface ................................................................................................................................ 28

Figure 4. Typical Straight Cable Connection ....................................................................................................................... 29

Figure 5. Typical Crossover Cable Connection ................................................................................................................... 29

Figure 6. 25MHz Crystal / Oscillator Reference Clock ........................................................................................................ 30

Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode .......................................................................... 30

Figure 8. KSZ8041NL/RNL Power and Ground Connections.............................................................................................. 31

Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 42

Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 43

Figure 11. MII Receive Timing (10Base-T) .......................................................................................................................... 44

Figure 12. MII Transmit Timing (100Base-TX)..................................................................................................................... 45

Figure 13. MII Receive Timing (100Base-TX)...................................................................................................................... 46

Figure 14. RMII Timing – Data Received from RMII ............................................................................................................ 47

Figure 15. RMII Timing – Data Input to RMII ....................................................................................................................... 47

Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 48

Figure 17. MDC/MDIO Timing.............................................................................................................................................. 49

Figure 18. Reset Timing....................................................................................................................................................... 50

Figure 19. Recommended Reset Circuit.............................................................................................................................. 51

Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 51

Figure 21. Reference Circuits for LED Strapping Pins......................................................................................................... 52

September 2010

7

M9999-090910-1.4

Share Link: