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LC662104A View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LC662104A Datasheet PDF : 13 Pages
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LC662104A, 662106A, 662108A
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Parameter
Operating supply voltage
Memory retention supply voltage
Input high-level voltage
Input low-level voltage
Operating frequency
(instruction cycle time)
[External clock input conditions]
Symbol
VDD
VDDH
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
fop
(Tcyc)
Conditions
VDD
VDD: During hold mode
P2, P3 (except for the P33/HOLD pin),
P4, P51, and P53: N-channel output transistor off
P33/HOLD, RES, OSC1:
N-channel output transistor off
P0, P1, P50, P52:
N-channel output transistor off
P2, P3 (except for the P33/HOLD pin),
RES, and OSC1: N-channel output transistor off
P33/HOLD: VDD = 1.8 to 5.5 V
P0, P1, P4, P5, TEST:
N-channel output transistor off
min
3.0
1.8
0.8 VDD
0.8 VDD
0.8 VDD
VSS
VSS
VSS
0.4
(10)
Ratings
typ
max
Unit Note
5.5 V
5.5 V
13.5 V
1
VDD
V
VDD
V
0.2 VDD
V
2
0.2 VDD
V
0.2 VDD
V
4.20 MHz
(0.95) (µs)
Frequency
Pulse width
fext
0.4
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
textH, textL (External clock input must be selected as the
100
oscillator circuit option.)
4.20 MHz
ns
Rise and fall times
textR, textF
30 ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 is applied to the P33/HOLD pin.
When ports P2 and P3 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications.
No. 5996-10/13
 

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