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DAC-08ENG View Datasheet(PDF) - ON Semiconductor

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DAC-08ENG Datasheet PDF : 14 Pages
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DAC−08 SERIES
Settling Time
The worst-case switching condition occurs when all bits
are switched on, which corresponds to a low-to-high
transition for all input bits. This time is typically 70 ns for
settling to within LSB for 8-bit accuracy. This time applies
when RL < 500 W and CO < 25 pF. The slowest single
switch is the least significant bit, which typically turns on
and settles in 65 ns. In applications where the DAC
functions in a positive-going ramp mode, the worst-case
condition does not occur and settling times less than 70 ns
may be realized.
Extra care must be taken in board layout since this
usually is the dominant factor in satisfactory test results
when measuring settling time. Short leads, 100 mF supply
bypassing for low frequencies, minimum scope lead
length, and avoidance of ground loops are all mandatory.
VIN
VREF = 10V
R14 = 5kW
IREF = 2mA
R15 = 5kW
5 6 7 8 9 10 11 12
14
4
DUT
15
2
16 3
1
C1
C2
C5
VS + = +15V
C3
Q1
R1 = 1000W R2 = 1000W
VADJ
D3
VOUT
VOUT
50W
D1
D2
C4 R3 = 500W
NOTES:
D1, D2 = IN6263 or equivalent
D3 = IN914 or equivalent
C1 = 0.01mF
VS − = −15V
C2, C3 = 0.1mF
Q1 = 2N3904
C4, C5 = 15pF and includes all probe and fixturing capacitance.
Figure 24. Settling Time and Propagation Delay
+VREF
MSB 2 3 4 5 6 7 LSB
RREF
IREF
5 6 7 8 9 10 11 12
(LOW T.C.)
14
4
IO
DAC-08
15
2
IO
3 16
13 1
V−
V+
CCOMP
0.1mF
0.1mF
NOTES:
) VREF 255
IFS [ RREF x 256 ; IO ) IO + IFS for all logic states
Figure 25. Basic DAC−08 Configuration
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