FC106 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
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FC106 Datasheet PDF : 0 Pages
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FC106
Pin
TX[0:9]
Level
CMOS
ZC+1, ZC-* CMOS
Description
TX[0:9] is the 10-bit parallel transmit data presented to the chip for serial-
ization and transmission onto the media. The order of transmission is TX[0]
through to TX[9].
These pins are used to control the input and output impedance in accor-
dance with the configuration outlined in Section 3.13:I/O impedance con-
trol on page 14.
1. indicates signals that are not included in the Fibre Channel 10-Bit Interface Specification.
7.2 Pin functions
Table 7.2
Pin Name
Vss
TX[0]
TX[1]
TX[2]
Vdd
TX[3]
TX[4]
TX[5]
TX[6]
Vdd
TX[7]
TX[8]
TX[9]
Vss
Vss/RS
NC/TDI
NC/TCK
Pin functions
Pin # I/O
1
-
2
I
3
I
4
I
5
-
6
I
7
I
8
I
9
I
10 -
11 I
12 I
13 I
14 -
15 (I)
16 (I)
17 (I)
pull up/
down
Description in standard running conditions
TEST
pins
-
Ground Pin
pd
Bit 0 of parallel transmit data (first bit sent)
pd
Bit 1 of parallel transmit data
pd
Bit 2 of parallel transmit data
-
Power Pin
pd
Bit 3 of parallel transmit data
pd
Bit 4 of parallel transmit data
pd
Bit 5 of parallel transmit data
pd
Bit 6 of parallel transmit data
-
Power Pin
pd
Bit 7 of parallel transmit data
pd
Bit 8 of parallel transmit data
pd
Bit 9 of parallel transmit data (last bit sent)
-
Ground Pin
pd
Must be tied to GND during normal operation. External
During power up, an internal circuit will
reset
automatically reset the chip. Nevertheless RS
allows a forced reset (when high), during normal
operation.
pd
Not connected
JTAG
scan in
pd
Not connected
Test clock
pin for
JTAG
26/32
September 98
Revision 1.2
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