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FC106 View Datasheet(PDF) - STMicroelectronics

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FC106
6 Timing Specifications
All AC measurements are made from the reference voltage level of the clock (1.4 volts), to
the valid input or output data levels.
6.1 Transmit interface timing and latency
Figure 6.1
Transmit interface timing and latency
REFCLK
1.4V
Tref
TX[0:9]
TX+
VALID
DATA 1
VALID
DATA 2
Tsu_tx
Th_tx
2.0V
VALID
1.4V
DATA 3
0.8V
bit 0 of parallel in-
put (TX0 of DATA 1)
Table 6.1
TELA
Transmit interface timing characteristics
Parameter Description
Min Typ Max
Units
Fref=1/Tref
F
tol
T
r
T
f
CLKJIT
DT
Tsu_tx
Th_tx
TX-Tr,Tf
TELA
Reference clock frequency
100
Frequency tolerance (dispersion between
100
REFCLK of transmitter and receiver chips)
REFCLK Clock Rise Time (0.8 to 2V)
0.6
REFCLK Clock Fall Time (0.8 to 2V)
0.6
REFCLK Jitter
REFCLK duty Cycle
40
Data set-up to a rising edge of REFCLK
0
Data hold after a rising edge of REFCLK
1.5
Parallel data rise and fall time (10 pF load)
0.6
Data Emission Latency (delay from the initial
-
10-bit word load to the serial transmission of bit 0)
106.25 110
-
+ 100
MHz
ppm
-
2.4
nS
-
2.4
nS
40
pS
-
60
%
-
-
ns
-
-
ns
-
3
ns
-
1 REFCLK
cycle + 8 ns
20/32
September 98
Revision 1.2
 

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