ADV7301AKST View Datasheet(PDF) - Analog Devices
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ADV7301AKST
Analog Devices
ADV7301AKST Datasheet PDF : 68 Pages
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ADV7300A/ADV7301A
MPU PORT DESCRIPTION
The ADV7300A/ADV7301A supports a 2-wire serial (I2C com-
patible) microprocessor bus driving multiple peripherals. Two
inputs, serial data (SDA) and serial clock (SCLK), carry informa-
tion between any device connected to the bus. Each slave device
is recognized by a unique address. The ADV7300A/ADV7301A
has four possible slave addresses for both read and write opera-
tions. These are unique addresses for each device and are
illustrated in Figures 15 and 16. The LSB sets either a read or
write operation. Logic Level “1” corresponds to a read operation,
while Logic Level “0” corresponds to a write operation. A1 is set
by setting the ALSB pin of the ADV7300A/ADV7301A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “1,” there is
greater input bandwidth on the I2C lines, which allows high
speed data transfers on this bus. When ALSB is set to “0,” there
is reduced input bandwidth on the I2C lines, which means that
pulses of less than 50 ns will not pass into the I2C internal con-
troller. This mode is recommended for noisy systems.
1
1
0
1
0
1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 WRITE
1 READ
Figure 15. ADV7300A Slave Address = D4h
0
1
0
1
0
1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 WRITE
1 READ
Figure 16. ADV7301A Slave Address = 54h
To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by estab-
lishing a start condition, defined by a high-to-low transition on
SDA, while SCLK remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start condition
and shift the next 8 bits (7-bit address + R/W Bit). The bits are
transferred from MSB down to LSB. The peripheral that rec-
ognizes the transmitted address responds by pulling the data line
low during the ninth clock pulse. This is known as an Ac-
knowledge Bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCLK lines waiting for the
start condition and the correct transmitted address. The R/W
Bit determines the direction of the data.
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7300A/ADV7301A acts as a standard slave device on
the bus. The data on the SDA pin is eight bits long, supporting
the 7-bit addresses plus the R/W Bit. It interprets the first byte
as the device address and the second byte as the starting
subaddress. The subaddress’s autoincrement allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, it will cause an imme-
diate jump to the idle condition. During a given SCLK high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7300A/ADV7301A will not issue an acknowledge and will
return to the idle condition. If in Autoincrement Mode the user
exceeds the highest subaddress, the following action will be taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the
ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7300A/ADV7301A, and the part will
return to the idle condition.
Before writing to the subcarrier frequency registers, it is a require-
ment that the ADV7300A/ADV7301A has been reset at least
once since power-up.
The four subcarrier frequency registers must be updated start-
ing with subcarrier frequency register 0. The subcarrier
frequency will not update until the last subcarrier frequency
register byte has been received by the ADV7300A/ADV7301A.
Figure 17 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 18 shows bus write and read sequences.
SDATA
SCLOCK S
1–7
8
9
1–7
8
9
START ADRR R/W ACK SUBADDRESS ACK
1–7
DATA
8
9
ACK
P
STOP
Figure 17. Bus Data Transfer
–14–
REV. A
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