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ADV7127KRU50 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7127KRU50 CMOS, 240 MHz 10-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7127KRU50 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7127
3.3 V TIMING SPECIFICATIONS1 (VAA = +3.0 V–3.6 V2, VREF = 1.235 V, RSET = 560 . All specifications TMINto TMAX3 unless
otherwise noted, TJ MAX = 110؇C)
Parameter
Min
Typ
Max
Units
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t74
Analog Output Transition Time, t85
Analog Output Skew, t96
7.5
ns
1.0
ns
15
ns
1
2
ns
CLOCK CONTROL
fCLK7
fCLK7
fCLK7
Data and Control Setup, t26
Data and Control Hold, t26
Clock Pulsewidth High, t4
Clock Pulsewidth Low t56
Clock Pulsewidth High t46
Clock Pulsewidth Low t56
Clock Pulsewidth High t46
Clock Pulsewidth Low t56
Pipeline Delay, tPD6
PSAVE Up Time, t106
PDOWN Up Time, t118
50
140
240
1.5
2.5
1.1
1.4
2.85
2.85
8.0
8.0
1.0
1.0
1.0
4
10
320
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
fMAX = 240 MHz
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 140 MHz
fMAX = 50 MHz
fMAX = 50 MHz
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
8This power-down feature is only available on the ADV7127 in the TSSOP package.
Specifications subject to change without notice.
CLOCK
t3
t4
t5
DIGITAL INPUTS
(D9–D0)
ANALOG OUTPUTS
(IOUT, IOUT )
t2
DATA
t1
t8
t6
t7
NOTES:
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL
SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
Figure 1. Timing Diagram
REV. 0
–7–
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