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ADV7127KRU50 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7127KRU50 CMOS, 240 MHz 10-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7127KRU50 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7127
3.3 V TSSOP SPECIFICATIONS1 (VAA = +3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMINto TMAX2
unless otherwise noted, TJ MAX = 110؇C)
Parameter
Min Typ Max
Units
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1
0.5
+1
–1
0.25 +1
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
PDOWN Input High Voltage3
2.0
0.8
2.1
PDOWN Input Low Voltage3
0.6
Input Current, IIN
PSAVE Pull-Up Current
–1
+1
20
Input Capacitance, CIN
10
ANALOG OUTPUTS
Output Current
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error4
2.0
18.5
0
+1.4
70
10
0
0
0
Bits
LSB
LSB
V
V
V
V
µA
µA
pF
mA
V
k
pF
% FSR
% FSR
RSET = 680
RSET = 680
RSET = 680
VIN = 0.0 V or VDD
Tested with DAC Output = 0 V
FSR = 17.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
VOLTAGE REFERENCE (Int.)5
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current6
Digital Supply Current6
Digital Supply Current6
Analog Supply Current
Analog Supply Current
Standby Supply Current
PDOWN Supply Current
Power Supply Rejection Ratio
1.12
1.235 1.35
1.235
1
2
2.5
4.5
4
6
22
25
5
2.6
3
20
0.1
0.5
V
V
mA
mA
mA
mA
mA
mA
µA
%/%
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560
RSET = 4933
PSAVE = Low, Digital and Control
Inputs at VDD
NOTES
1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3This power-down feature is only available on the ADV7127 in the TSSOP package.
4Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
5Internal voltage reference is available only on the ADV7127 TSSOP package.
6Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
Specifications subject to change without notice.
REV. 0
–5–
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