datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

ADV7125JST330 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125JST330 CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125JST330 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7125
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic
Function
1, 2, 14, 15, 25, GND
26, 39, 40
Ground. All GND pins must be connected.
3–10,
16–23,
41–48
11
12
G0–G7,
B0–B7,
R0–R7
BLANK
SYNC
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
be connected to either the regular PCB power or ground plane.
Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the
analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the
rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.
Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches
off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the SYNC input should be tied to logical zero.
13, 29, 30
24
27, 31, 33
VAA
CLOCK
IOR, IOG, IOB
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These
RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75 load. If the complementary outputs are not required, these outputs should be
tied to ground.
28, 32, 34
IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of
directly driving a doubly terminated 75 coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.
35
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF
ceramic capacitor must be connected between COMP and VAA.
36
VREF
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
37
RSET
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC
is connected to IOG) is given by:
( ) ( ) ( ) RSET Ω = 11,445 ×VREF V / IOG mA
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,444.8 × VREF (V ) / RSET ()(SYNC being asserted)
( ) ( ) ( ) IOR , IOB mA = 7,989.6 ×VREF V / RSET
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used,
i.e., SYNC tied permanently low.
38
PSAVE
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this
pin is active.
REV. 0
–7–
Direct download click here
 

Share Link : ADI
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]