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ADV7125KST50 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125KST50 CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125KST50 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7125
5 V TIMING SPECIFICATIONS1 (VAA = 5 V ± 5%2, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMIN to TMAX3,
unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t74
Analog Output Transition Time, t85
Analog Output Skew, t96
5.5
ns
1.0
ns
15
ns
1
2
ns
CLOCK CONTROL
fCLK7
fCLK7
fCLK7
Data and Control Setup, t16
Data and Control Hold, t26
Clock Period, t3
Clock Pulsewidth High, t46
Clock Pulsewidth Low, t56
Clock Pulsewidth High, t46
Clock Pulsewidth Low, t56
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Pipeline Delay, tPD6
PSAVE Up Time, t106
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
1.0
2
50
MHz
50 MHz Grade
140
MHz
140 MHz Grade
240
MHz
240 MHz Grade
ns
ns
ns
ns
fCLK_MAX = 240 MHz
ns
fCLK_MAX = 240 MHz
ns
fCLK_MAX = 140 MHz
ns
fCLK_MAX = 140 MHz
ns
fCLK_MAX = 50 MHz
ns
fCLK_MAX = 50 MHz
1.0
Clock Cycles
10
ns
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. 0
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