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ADV7125KST140 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7125KST140 CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7125KST140 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7125
3.3 V ELECTRICAL CHARACTERISTICS1
(VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications
TMIN to TMAX2, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Test Conditions2
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
–1
Differential Nonlinearity
–1
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Input Current, IIN
–1
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current
2.0
Output Current
2.0
DAC-to-DAC Matching
Output Compliance Range, VOC
0
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error3
8
± 0.5
+1
± 0.25 +1
0.8
+1
20
10
26.5
18.5
1.0
1.4
70
10
0
0
0
Bits
LSB
LSB
RSET = 680
RSET = 680
RSET = 680
V
V
µA
VIN = 0.0 V or VDD
µA
pF
mA
mA
%
V
k
pF
% FSR
% FSR
Green DAC, Sync = High
R/G/B DAC, Sync = Low
Tested with DAC Output = 0 V
FSR = 18.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
VOLTAGE REFERENCE (Int.)
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current4
Digital Supply Current4
Digital Supply Current4
Digital Supply Current4
Analog Supply Current
Analog Supply Current
Standby Supply Current
Power Supply Rejection Ratio
1.12
1.235
1.35
V
1.235
V
2.2
5.0
mA
fCLK = 50 MHz
6.5
12.0
mA
fCLK = 140 MHz
11
15
mA
fCLK = 240 MHz
16
mA
fCLK = 330 MHz
67
72
mA
RSET = 560
8
mA
RSET = 4933
2.1
5.0
mA
PSAVE = Low, Digital, and Control
Inputs at VDD
0.1
0.5
%/%
NOTES
1These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF/RSET × K × (FFH) × 4 and K = 7.9896.
4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
Specifications subject to change without notice.
REV. 0
–3–
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