ADV7125JST240 View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADV7125JST240 Datasheet PDF : 12 Pages
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ADV7125
Analog Signal Interconnect
The ADV7125 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly termi-
nated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7125 to minimize reflections.
Additional information on PCB design is available in an application
note entitled Design and Layout of a Video Graphics System for
Reduced EMI. This application note is available from Analog
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).
0.1F
5V (VAA)
41–48
VIDEO
DATA
INPUTS
3–10
16–23
COMP
R7–R0
VAA
VREF
POWER SUPPLY DECOUPLING (0.1F AND 0.01F
CAPACITOR FOR EACH VAA GROUP)
13, 29,
30
0.1F 0.01F
L1
VAA
(FERRITE BEAD)
ANALOG GROUND PLANE
0.1F
5V (VAA)
10F
G7–G0
RSET
IOR
B7–B0
IOG
RSET
530⍀
COAXIAL CABLE
75⍀
MONITOR
(CRT)
75⍀
75⍀
IOB
ADV7125
SYNC
IOR
BLANK
IOG
CLOCK
IOB
PSAVE
GND
75⍀ 75⍀ 75⍀
75⍀
COMPLEMENTARY
OUTPUTS
BNC
CONNECTORS
1, 2, 14, 15,
25, 26, 39, 40
VCC
33F
Figure 7. Typical Connection Diagram
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
0.75
0.60
0.45
PIN 1
INDICATOR
48
1
9.00 BSC
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
SEATING
PLANE
0.20
0.09
7؇
3.5؇
0؇
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90؇ CCW
VIEW A
TOP VIEW
(PINS DOWN)
12
13
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MS-026BBC
37
36
7.00
BSC
25
24
0.27
0.22
0.17
–12–
REV. 0
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