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ADF4360-2BCPRL View Datasheet(PDF) - Analog Devices

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ADF4360-2BCPRL
ADI
Analog Devices ADI
ADF4360-2BCPRL Datasheet PDF : 24 Pages
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ADF4360-2
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When a lock is detected, the output is high with narrow low-
going pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
Figure 13. MUXOUT Circuit
DGND
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs are DB1 and
DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
Control Latch
0
1
R Counter
1
0
N Counter (A and B)
1
1
Test Mode Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and is
connected to an internal reference voltage.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1600
1700 1800 1900 2000 2100 2200
FREQUENCY (MHz)
Figure 14. Frequency vs. VTUNE, ADF4360-2
2300
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by Bit BSC1 and Bit BSC2 in the R counter latch.
Where the required PFD frequency exceeds 1 MHz, the divide ratio
should be set to allow enough time for correct band selection.
After band selection, normal PLL action resumes. The nominal
value of KV is 57 MHz/V, or 28 MHz/V if divide-by-2 operation
is selected (by programming DIV2 [DB22] high in the N
counter latch). The ADF4360 family contains linearization
circuitry to minimize any variation of the product of ICP and KV.
Rev. B | Page 10 of 24
 

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