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ADF4106BCPZ-R7 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADF4106BCPZ-R7
ADI
Analog Devices ADI
ADF4106BCPZ-R7 Datasheet PDF : 24 Pages
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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADF4106
RSET 1
16 VP
CP 2
15 DVDD
CPGND 3 ADF4106 14 MUXOUT
AGND 4 TOP VIEW 13 LE
(Not to Scale)
RFINB 5
12 DATA
RFINA 6
11 CLK
AVDD 7
10 CE
REFIN 8
9 DGND
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
Figure 3. 16-Lead TSSOP Pin Configuration
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
PIN 1
INDICATOR
ADF4106
TOP VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Pin No.
TSSOP LFCSP Mnemonic Function
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I CP MAX
= 25.5
RSET
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
6
5
RFINA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7
6, 7
AVDD
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
9, 10 DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
14
15
MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
15
16, 17 DVDD
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP
Exposed Pad. The exposed pad must be connected to AGND.
Rev. E | Page 7 of 24
 

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