ADF4001BRUZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

ADF4001BRUZ-RL

200 MHz Clock Generator PLL

Analog Devices 

Table IV. N Counter Latch Map

ADF4001

RESERVED

13-BIT N COUNTER

RESERVED

CONTROL

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

X G1 N13 N12 N11 N10 N9 N8

N7 N6

N5 N4 N3 N2

N1

X

XXX

X X C2 (0) C1 (1)

X = DON’T CARE

N13

N12

N11

N3

N2

N1

N COUNTER DIVIDE RATIO

0

0

0

..........

0

0

1

1

0

0

0

..........

0

1

0

2

0

0

0

..........

0

1

1

3

0

0

0

..........

1

0

0

4

.

.

.

..........

.

.

.

.

.

.

.

..........

.

.

.

.

.

.

.

..........

.

.

.

.

1

1

1

..........

1

0

0

8188

1

1

1

..........

1

0

1

8189

1

1

1

..........

1

1

0

8190

1

1

1

..........

1

1

1

8191

F4 (FUNCTION LATCH)

FASTLOCK ENABLE CP GAIN OPERATION

0

0

CHARGE PUMP CURRENT SETTING

1 IS PERMANENTLY USED

0

1

CHARGE PUMP CURRENT SETTING

2 IS PERMANENTLY USED

1

0

CHARGE PUMP CURRENT SETTING

1 IS USED

1

1

CHARGE PUMP CURRENT IS

SWITCHED TO SETTING 2. THE

TIME SPENT IN SETTING 2 IS

DEPENDENT ON WHICH FASTLOCK

MODE IS USED. SEE FUNCTION

LATCH DESCRIPTION.

THESE BITS ARE NOT USED

BY THE DEVICE AND ARE

DON’T CARE BITS.

REV. B

–9–

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