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ADF4001BRU View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADF4001BRU
ADI
Analog Devices ADI
ADF4001BRU Datasheet PDF : 17 Pages
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ADF4001
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
DGND
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to 0, digital
lock detect is set high when the phase error on three consecutive
phase detector cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 knominal. When lock has been detected,
this output will be high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4001 digital section includes a 24-bit input shift regis-
ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a sum-
mary of how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
R Counter
0
1
N Counter
1
0
Function Latch
1
1
Initialization Latch
Table II. ADF4001 Family Latch Summary
REFERENCE COUNTER LATCH
RESERVED
TEST
MODE
BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
X
X
X LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9
R8 R7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
N COUNTER LATCH
RESERVED
CP
GAIN
13-BIT N COUNTER
RESERVED
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
X
X G1 N13 N12 N11 N10 N9 N8 N7 N6
N5 N4
N3
N2 N1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
XX X
X
X C2 (0) C1 (1)
RESERVED
CURRENT
SETTING
2
CURRENT
SETTING
1
FUNCTION LATCH
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
X
X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
F4 F3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
INITIALIZATION LATCH
RESERVED
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
F4 F3
F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)
X = DON’T CARE
REV. B
–7–
 

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