ADF4001BCPZ View Datasheet(PDF) - Analog Devices

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ADF4001BCPZ

200 MHz Clock Generator PLL

Analog Devices 

ADF4001

COHERENT CLOCK GENERATION

When testing A/D converters, it is often advantageous to use a

coherent test system, that is, a system that ensures a specific

relationship between the A/D converter input signal and the

A/D converter sample rate. Thus, when doing an FFT on this

data, there is no longer any need to apply the window weighting

function. Figure 8 shows how the ADF4001 can be used to handle

all the possible combinations of the input signal frequency and

sampling rate. The first ADF4001 is phase locked to a VCO. The

output of the VCO is also fed into the N divider of the second

ADF4001. This results in both ADF4001s being coherent with

the REFIN. Since the REFIN comes from the signal generator, the

MUXOUT signal of the second ADF4001 is coherent with the fIN

frequency to the ADC. This is used as fS, the sampling clock.

SINE

OUTPUT

BRUEL &

KJAER

MODEL 1051

fIN

fS = (fIN ؋ N1)/(R1 ؋ N2)

SQUARE REFIN

OUTPUT

،R1

،N1

ADF4001

CPRF LOOP

FILTER

RFIN

A/D

AIN CONVERTER

UNDER

TEST

SAMPLING

CLOCK

fS

VCO

100MHz

،N2

ADF4001

RFIN

MUXOUT

NC7S04

Figure 8. Coherent Clock Generator

TRI-BAND CLOCK GENERATION CIRCUIT

In multiband applications, it is necessary to realize different

clocks from one master clock frequency. For example, GSM

uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and

CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to

use the ADF4001 to generate GSM, WCDMA, and CDMA

system clocks from a single 52 MHz master clock. The low RF

fMIN specification and the ability to program R and N values as

low as Ϭ 1 makes the ADF4001 suitable for this. Other fOUT

clock frequencies can be realized using the formula

( ) fOUT = REFIN × N ÷ R

SHUTDOWN CIRCUIT

The circuit in Figure 10 shows how to shut down both the

ADF4001 and the accompanying VCO. The ADG702 switch

goes open circuit when a Logic 1 is applied to the IN input.

The low cost switch is available in both SOT-23 and micro

SOIC packages.

REFIN

،R1

،4

CPRF LOOP

FILTER

13MHz SYSTEM

CLOCK FOR GSM

VCXO

13MHz

52MHz

MASTER

CLOCK

،1

،N1

ADF4001

،R2

REFIN

،1300

،486

،N2

ADF4001

REFIN

،R3

،65

RFIN

CPRF LOOP

FILTER

19.44MHz SYSTEM

CLOCK FOR WCDMA

VCXO

19.44MHz

RFIN

CPRF LOOP

FILTER

19.2MHz SYSTEM

CLOCK FOR CDMA

VCXO

19.2MHz

،24

RFIN

،N3

ADF4001

Figure 9. Tri-Band System Clock Generation

VP

POWER-DOWN CONTROL

S VDD

VDD

RFOUT

IN

ADG702

D GND

100pF

7

15 16

10

AVDD DVDD VP CE

2

CP

FREFIN

1

RSET

LOOP

FILTER

10k⍀

ADF4001

VCC

VCO

OR

VCXO

GND

100pF 18⍀

18⍀

18⍀

100pF

RFINA 6

5

RFINB

51⍀

CPGND AGND DGND

3

4

9

100pF

DECOUPLING CAPACITORS AND INTERFACE

SIGNALS HAVE BEEN OMITTED FROM THE

DIAGRAM IN THE INTEREST OF GREATER CLARITY.

Figure 10. Local Oscillator Shutdown Circuit

–14–

REV. B

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