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ADC08004-1LCD View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
ADC08004-1LCD CMOS 8-bit A/D converters Philips
Philips Electronics Philips
ADC08004-1LCD Datasheet PDF : 18 Pages
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Philips Semiconductors
CMOS 8-bit A/D converters
Product data
ADC0803/0804
Full Scale Adjustment
Full scale gain is adjusted by applying any desired offset voltage to
VIN(–), then applying the VIN(+) a voltage that is 1-1/2 LSB less than
the desired analog full-scale voltage range and then adjusting the
magnitude of VREF/2 input voltage (or the VCC supply if there is no
VREF/2 input connection) for a digital output code which just
changes from 1111 1110 to 1111 1111. The ideal VIN(+) voltage for
this full-scale adjustment is given by:
VIN())
+
VIN(*) * 1.5
x
VMAX * VMIN
255
where:
VMAX = high end of analog input range (ground referenced)
VMIN = low end (zero offset) of analog input (ground referenced)
CLOCKING OPTION
The clock signal for these A/Ds can be derived from external
sources, such as a system clock, or self-clocking can be
accomplished by adding an external resistor and capacitor, as
shown in Figure 11.
Heavy capacitive or DC loading of the CLK R pin should be avoided
as this will disturb normal converter operation. Loads less than 50pF
are allowed. This permits driving up to seven A/D converter CLK IN
pins of this family from a single CLK R pin of one converter. For
larger loading of the clock line, a CMOS or low power TTL buffer or
PNP input logic should be used to minimize the loading on the CLK
R pin.
Restart During a Conversion
A conversion in process can be halted and a new conversion began
by bringing the CS and WR inputs low and allowing at least one of
them to go high again. The output data latch is not updated if the
conversion in progress is not completed; the data from the
previously completed conversion will remain in the output data
latches until a subsequent conversion is completed.
Continuous Conversion
To provide continuous conversion of input data, the CS and RD
inputs are grounded and INTR output is tied to the WR input. This
INTR/WR connection should be momentarily forced to a logic low
upon power-up to insure circuit operation. See Figure 10 for one
way to accomplish this.
DRIVING THE DATA BUS
This CMOS A/D converter, like MOS microprocessors and
memories, will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry tied to the data bus will add to
the total capacitive loading, even in the high impedance mode.
There are alternatives in handling this problem. The capacitive
loading of the data bus slows down the response time, although DC
specifications are still met. For systems with a relatively low CPU
clock frequency, more time is available in which to establish proper
logic levels on the bus, allowing higher capacitive loads to be driven
(see Typical Performance Characteristics).
At higher CPU clock frequencies, time can be extended for I/O
reads (and/or writes) by inserting wait states (8880) or using
clock-extending circuits (6800, 8035).
Finally, if time is critical and capacitive loading is high, external bus
drivers must be used. These can be 3-State buffers (low power
Schottky is recommended, such as the N74LS240 series) or special
higher current drive products designed as bus drivers. High current
bipolar bus drivers with PNP inputs are recommended as the PNP
input offers low loading of the A/D output, allowing better response
time.
POWER SUPPLIES
Noise spikes on the VCC line can cause conversion errors as the
internal comparator will respond to them. A low inductance filter
capacitor should be used close to the converter VCC pin and values
of 1 µF or greater are recommended. A separate 5 V regulator for
the converter (and other 5 V linear circuitry) will greatly reduce
digital noise on the VCC supply and the attendant problems.
WIRING AND LAYOUT PRECAUTIONS
Digital wire-wrap sockets and connections are not satisfactory for
breadboarding this (or any) A/D converter. Sockets on PC boards
can be used. All logic signal wires and leads should be grouped or
kept as far as possible from the analog signal leads. Single wire
analog input leads may pick up undesired hum and noise, requiring
the use of shielded leads to the analog inputs in many applications.
A single-point analog ground separate from the logic or digital
ground points should be used. The power supply bypass capacitor
and the self-clocking capacitor, if used, should be returned to digital
ground. Any VREF/2 bypass capacitor, analog input filter capacitors,
and any input shielding should be returned to the analog ground
point. Proper grounding will minimize zero-scale errors which are
present in every code. Zero-scale errors can usually be traced to
improper board layout and wiring.
2002 Oct 17
7
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