A43L0616AV View Datasheet(PDF) - AMIC Technology

Part Name

Description

View to exact match

A43L0616AV

512K X 16 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

A43L0616A

Pin Descriptions

Symbol

CLK

CS

CKE

A0~A10/AP

BA

Name

Description

System Clock

Active on the positive going edge to sample all inputs.

Chip Select

Disables or Enables device operation by masking or enabling all inputs except CLK,

CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

Clock Enable

CKE should be enabled at least one clock + tss prior to new command.

Disable input buffers for power down in standby.

Address

Row / Column addresses are multiplexed on the same pins.

Row address : RA0~RA10, Column address: CA0~CA7

Selects bank to be activated during row address latch time.

Bank Select Address

Selects band for read/write during column address latch time.

RAS

Latches row addresses on the positive going edge of the CLK with RAS low.

Row Address Strobe

Enables row access & precharge.

CAS

Column Address

Strobe

WE

Write Enable

L(U)DQM

Data Input/Output

Mask

DQ0-15

Data Input/Output

VDD/VSS

Power

Supply/Ground

VDDQ/VSSQ

Data Output

Power/Ground

NC/RFU

No Connection

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and Row precharge.

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power Supply: +3.3V±0.3V/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

(September, 2004, Version 2.2)

3

AMIC Technology, Corp.

Share Link: